COMPSCI 110 Cheatsheet · Introduction to Computer Systems

University of Auckland · A4 cheat sheet for the final exam. Semester Two examination period, 29 October – 16 November 2026. Full COMPSCI 110 study guide →

A4 landscape · ~7pt body · 6 columns · ink + yellow onlyONE A4 NOTE SHEET · COMPSCI 110 · S2 2026
COMPSCI 110
Introduction to Computer Systems
School of Computer Science · University of Auckland · Stage I
COMPSCI 110 cheatsheet QR code – open the full COMPSCI 110 study guide
Full guide + ask Sia about COMPSCI 110
SIDE 1/2   EXAM MAP · METHODS · RULES · DECISIONSONE A4 NOTE SHEETModules 1–4, 6–11 · Final Exam 50%

01 · Exam map course.json · brief

Final 50%Test 20%Assignments 20%Essays 8%2
AssessmentWeightWhat matters here
Final Exam50%Modules 1–4, 6–11; Inspera IIB Mode D; 36 questions / 50 marks
Mid-Semester Test20%Earlier modules; Module 5 belongs here, not the final
Assignments20%Practical grouping
Essays8%
Tutorials2%

“An A4-cheat sheet (typed or handwritten) can be brought into the exam hall.” (COMPSCI 110 exam revision slides, Semester Two 2026)

Scope Final weighting: OS 8 marks; Compilers 7; Security 6; Turing 6; Networks 5; AI 5; Binary 4; Logic, Organisation and Assembly 3 each. Spend time in that order, but bank every mechanical mark.

02 · Binary toolkit M1 · CH 1

234₁₀ = 11101010₂ 1110 = E1010 = A 4-bit groups → EA₁₆ 3-bit groups → 11|101|010 = 352₈
Source redraw: group from the right; 4 bits per hex digit, 3 per octal digit.
Positional value / sizing(dₖ…d₀)ᵦ = Σ dᵢbⁱ
k distinct patterns need ⌈log₂k⌉ bits
N address bits select 2ᴺ cells
TaskProcedureCheck
Decimal → binaryRepeatedly ÷2; record remainder; read bottom-upOdd ends 1; even ends 0
Fraction → binaryRepeatedly ×2; record integer parts top-down0.1875₁₀ = 0.0011₂
ShiftLeft one place ×2; right one place ÷2Bits falling off are lost
Fixed-width sumAdd right-to-left; 1+1 writes 0, carries 1Overflow when result cannot fit

Signed representations

FormNegativen-bit range / zero
Sign-magnitudeFlip sign bit±(2ⁿ⁻¹−1); two zeros
One's complementInvert all bits±(2ⁿ⁻¹−1); two zeros
Two's complementInvert + 1−2ⁿ⁻¹…2ⁿ⁻¹−1; one zero
Two's-complement subtractiona − b = a + (−b) = a + ~b + 1
Fix width → invert b → carry-in 1 → add → discard carry out.

03 · Logic → circuit M2 · CH 2

A BANDORNANDNOR
0 00011
0 10110
1 00110
1 11100

NOT flips 0↔1. NAND and NOR are functionally complete; tie their inputs together to make NOT. An n-input table has 2ⁿ rows.

De Morgan¬(A + B) = ¬A · ¬B
¬(A · B) = ¬A + ¬B
truth table take Y=1 rows OR terms row 00 → ¬A·¬B · row 01 → ¬A·B row 11 → A·B Y=(¬A·¬B)+(¬A·B)+(A·B)
Source redraw: SOP means one product for every true row; bar each input that is 0.

Hardware rules

ElementInputs → outputs / rule
Full adderaᵢ,bᵢ,cᵢ → sum sᵢ and carry cᵢ₊₁; chain carry to next bit
SubtractInvert b and set initial carry-in 1
Multiplexor2ᴺ inputs, N selectors, 1 output
DecoderN inputs, 2ᴺ outputs
SR latch00 hold; 10 set; 01 reset; 11 forbidden

Exam move From a supplied truth table: circle every output-1 row; write all variables in each AND term; bar only the 0 inputs; OR every term. Simplify only if asked.

04 · Stored-program machine M3 · CH 3

PC MAR MEMORY MDR IR 12 address2 data3 4 · PC ← PC + 1 → DECODE
Source redraw: fetch order is PC→MAR; cell→MDR; MDR→IR; increment PC; then decode and execute.
RegisterRole
PCAddress of next instruction
IRInstruction now executing
MARAddress accessed: the “where”
MDRData fetched/stored: the two-way “what”

Von Neumann: one memory holds instructions and data; subsystems are Memory, I/O, ALU and Control Unit; CPU = ALU + CU. Shared sequential traffic causes the bottleneck. Fetch preserves; store overwrites.

05 · Assembly / machine code M4 · CH 4

one 16-bit instruction word 11010000 0000 1001 opcode · INaddress 9 · D009₁₆
Source redraw: high 4 bits = opcode; low 12 = address. One instruction occupies one cell.
InstructionOpcodeEffect
LOAD X0000CON(X) → R
STORE X0001R → CON(X)
ADD X0011R + CON(X) → R
SUBTRACT X0101R − CON(X) → R
COMPARE X0111Set GT/EQ/LT flags
HALT1111Stop; address 000…0

Use supplied Figure 6.5: lookup → 12-bit address → concatenate → hex nibbles. Arithmetic uses one register R and 16-bit two's complement.

Desk-check / assemble

  1. After every line record R, changed memory and GT/EQ/LT.
  2. .BEGIN/.END/.DATA are directives; LABEL: .DATA 0 binds an address.
  3. Pass 1 builds label→address; pass 2 inserts opcodes/addresses and emits words. This resolves forward labels.

Trap Do not “remember” an opcode when Figure 6.5 is supplied. Read it; then keep opcode in the top nibble and pad the operand to exactly 12 bits.

06 · Network calculations M6 · CH 6

processd_proc queued_queue transmitL/R propagated/s d_n = proc + queue + L/R + d/s throughput ≈ min(all link rates)
Source redraw: transmission depends on bits/rate; propagation depends on distance/speed.
Use when the question givespacket length L and rate R: d_trans = L/R
distance d and signal speed s: d_prop = d/s
s ≈ 2×10⁸ m/s; convert Mbit→bits and km→m first.
ContrastAB
SwitchingPacket: dynamic; queue/dropCircuit: fixed reserved rate
Path actionForwarding: local tableRouting: network path
Delay testBigger packet ↑ d_transLonger link ↑ d_prop

07 · Compiler decision chain M7 · CH 7 · 7 marks

I · scantokens II · parsetree III · meaning+ code IV · opt.efficient chars → tokens → tree → code form → grammar → meaning→ speed/space
Source redraw: the phase tells you which error or artefact is being tested.
PhaseInput → outputDoes / does not
I Lexicalcharacters → tokensLongest valid token; discards whitespace/comments; does not check syntax
II Parsingtokens + grammar → parse treeChecks syntactic form using BNF productions
III Semantic + generationtree + records → instructionsTypes, names, addresses and meaning; emits code
IV Optimisationcode → improved codeImproves time or space without changing meaning

Tokenise under pressure

  1. Scan left→right. Take the longest valid token.
  2. Classify: keyword; identifier/symbol; operator; bracket; number; literal; terminator/symbol.
  3. Discard spaces and comments. == is one operator token and differs from assignment =.
  4. Count the list. An illegal arrangement still tokenises; the parser rejects its grammar later. A misplaced else remains a keyword.
SourceClass
ifkeyword
( )brackets
a, b, answersymbols / identifiers
==, =operators; each is one token
42number
;symbol / terminator

BNF: productions expand non-terminals into terminals/non-terminals. A parse tree is valid only if its leaves match the token stream and its root reaches the grammar's goal symbol. Syntax asks whether the form is legal; semantics asks whether that legal form makes sense.

Assembler / compiler splitassembly → one machine instruction per source instruction; table lookup + labels
high-level → many machine instructions; lexical + syntax + meaning

Mark check If the prompt says “scanner”, do not repair syntax. If it says “parser”, use the supplied grammar. If it says “semantic”, discuss meaning/type/name records, not punctuation.

09 · OS scheduling M8 · CH 8 · 8 marks

CREATE READY RUN FINISH WAIT scheduler chooses from ready queue
Source redraw: a process is a program in execution; waiting means blocked, not deadlocked.
PolicyRuleConsequence
FCFSLongest-waiting process runs to completionSimple; long first job causes convoy effect
Round-RobinRun ≤ quantum; unfinished job is preempted to queue tailResponsive/fair; more switches
Round-Robin method1 build exact timeline by queue order
2 read each completion time
3 if all arrive at 0: waiting = completion − burst
4 average = Σ waiting / process count
Context-switch costCPU efficiency = slice / (slice + switch time) × 100%
larger slice ↑ efficiency but ↓ responsiveness; tiny slice wastes time switching.

A context switch saves PC, registers and resource handles, then loads the next process. Useful work pauses. If arrival times are not all zero, do not use the shortened waiting formula without accounting for arrival.

OS managers: process, memory, device, file and network managers plus the command interpreter. The ready queue holds runnable processes; the waiting queue holds processes blocked on an event or I/O.

Deadlock decision

P1 R2 P2 R1 P1→R2→P2→R1→P1
Source redraw: process→resource means waiting; resource→process means allocated.
RAG testConclusion
One unit per resource + cycleDeadlock
Multiple units + cycleNecessary, not sufficient; check whether any process can still finish
No cycleNo deadlock

Trap A process merely waiting for I/O is not deadlocked. Deadlock is permanent circular waiting: each holds something the next needs and none can proceed.

10 · Cryptography chooser M9 · CH 9 · 6 marks

SYMMETRICAliceencrypt K→ cipher →Bob K PUBLIC KEYAliceBob public→Bob private
Source redraw: symmetric is fast but shares a secret; public/private keys solve distribution.
AxisChoose / remember
ProcessingBlock: fixed block/diffusion. Stream: elementwise.
KeysSymmetric: one shared secret. Asymmetric: public/private pair.
SystemsDES 56/64; 3DES ≈168; AES keys 128/192/256, block 128. RSA/Diffie–Hellman are public-key.
CertificateTrusted binding: identity ↔ public key.
Matrix block cipherA=0…Z=25; row vector V
encrypt C = V·M mod 26
decrypt V = C·M′ mod 26, where M·M′ = I mod 26

Caesar: 25 shifts + preserved frequencies ⇒ brute force/frequency attack. Matrix blocks add diffusion.

11 · Turing trace M10 · CH 10 · 6 marks

(i,j,k,s,dir): read j · write k · state s · move b101bb head starts on leftmost non-blank · state 1
Source redraw: tape is infinite both ways; it is input, working memory and output.
  1. Record state + symbol; choose the unique matching rule.
  2. Write field 3; go to state 4; move field 5.
  3. No match ⇒ HALT; repeating a configuration indicates a loop.

Valid: no duplicate (state,symbol) left sides. Church–Turing: any effectively computable function is Turing-computable; thesis, not theorem.

12 · AI concept distinctions M11 · CH 11 · 5 marks

ConceptDiscriminator
Turing testText imitation; judge cannot reliably distinguish person/machine.
WinogradPronoun needs commonsense; wording can flip referent.
Neural netLayered units + weighted links.
Back-propagationError moves backward to adjust weights; no arithmetic here.

Trap Turing tests behaviour, not inner mechanism; Winograd tests meaning, not grammar alone.

Your exam allows one A4 sheet of notes, both sides. Check on the LMS whether printed notes are accepted; if they must be handwritten, copy it.
asksia.ai/cheatsheet/auckland-compsci110 · Full COMPSCI 110 study guide →Forward this to your tutorial group
v2 · 2026-10-16
Semester Two examination period, 29 October – 16 November 2026.
Shared by ________
COMPSCI 110
Worked Drills · Traps · Fast Recall
Introduction to Computer Systems · University of Auckland
COMPSCI 110 cheatsheet QR code – open the full COMPSCI 110 study guide
Full guide + ask Sia about COMPSCI 110
SIDE 2/2   WORKED EXAMPLES · ERROR CHECKS · METHOD CHOOSERONE A4 NOTE SHEETUse source values · carry every calculation to the answer

13 · Worked: −9 in 5-bit two's complement M1 · worked example

Question: represent −9, verify with +9, and state the signed range.

+9 = 01001 flip 10110 +1 10111 1 00000 → drop carry → 00000 5-bit range: −16 … +15
Every value is width-sensitive. The leading 1 is a sign bit only because the width is fixed.
  1. +9: 01001₂.
  2. Invert: 10110₂.
  3. Add 1: 10111₂, so this encodes −9.
  4. Verify: 01001 + 10111 = 1 00000; discard carry → 0. Range = −2⁴…2⁴−1 = −16…+15.
Answer−9₁₀ = 10111₂ in 5-bit two's complement.

Trap 10110 is one's complement, off by one. The range is asymmetric: −16 exists but +16 does not.

14 · Worked: SOP from a table M2 · worked example

ABYProduct when Y=1
001¬A·¬B
011¬A·B
100—
111A·B
Y=(¬A·¬B)+(¬A·B)+(A·B) ¬A(¬B + B) + A·B = ¬A + A·B = ¬A + B
The direct SOP earns the construction marks; simplification is a cross-check unless requested.
  1. Select rows 00, 01, 11 because Y=1.
  2. Write one AND term per row, barring each 0 input.
  3. OR all terms: (¬A·¬B) + (¬A·B) + (A·B).
  4. Optional check: first two terms = ¬A; result simplifies to ¬A + B and reproduces 1,1,0,1.

Trap Do not bar the 1s; bar the 0s. Do not omit an output-1 row. A combinational circuit depends only on current inputs; an SR latch stores state.

15 · Binary micro-checks M1 · body text

PromptCorrect result / reason
0101₂ + 0011₂1000₂; carry right-to-left
0.1001₂½ + 1⁄16 = 9⁄16
1101₂ << 31101000₂; ×8
4-bit +7 + 10111→1000 = −8 in two's complement

16 · Worked: assembly → machine M4 · worked example

Given: Y at address 13; THREE at 14; X at 12. Translate LOAD Y · ADD THREE · STORE X · HALT.

opcode 4 bits | address 12 bits 00000000 0000 1101 LOAD Y → 0000 0000 0000 1101 = 000D₁₆
Source redraw: pad the address, concatenate, then read four-bit hex nibbles.
Source16-bit binaryHex
LOAD Y0000 0000 0000 1101000D
ADD THREE0011 0000 0000 1110300E
STORE X0001 0000 0000 1100100C
HALT1111 0000 0000 0000F000
  1. Lookup opcodes: LOAD 0000; ADD 0011; STORE 0001; HALT 1111.
  2. Write 13, 14, 12 as 12-bit addresses; no-operand HALT uses zeros.
  3. Join 4+12 bits. Group into nibbles only after the 16-bit word is complete.

Trap Addresses are values 13, 14, 12, not the values stored in Y, THREE and X.

17 · Worked: field sizing M3 · worked example

Machine: 16-bit IR, 16 instructions, 16 registers. Can OPCODE REG1 REG2 REG3 fit?

opcode4 bits R14R24R34 4 + 4 + 4 + 4 = 16 · exact fit
Different questions size different fields: instruction count → opcode; register count → register field.
  1. 16 operations: 2⁴=16 → opcode = 4 bits.
  2. 16-bit word − 4 = 12 operand bits.
  3. 16 registers: 2⁴=16 → each register field = 4 bits.
  4. 4-bit opcode + three 4-bit registers = 16 bits: fits exactly.
Answeropcode 4 bits; operands 12 bits total; one register 4 bits; three-register format fits.

18 · Fetch trace scaffold M3 · body text

StartMicro-stepAfter
PC=120PC→MARMAR=120
cell 120 = LOAD 45FETCHMDR=LOAD 45
MDR setMDR→IRIR=LOAD 45
PC=120PC←PC+1PC=121
cell 45=7execute LOADR=7

19 · Worked: link delay + bottleneck M6 · worked example

Given: L=3 Mbit; R=1.5 Mbps; distance=3000 km; s=2×10⁸ m/s; later link=1 Mbps.

TRANSMISSION3×10⁶ / 1.5×10⁶ = 2 s PROPAGATION3×10⁶ / 2×10⁸ = 0.015 s = 15 ms throughput = min(1.5, 1) = 1 Mbps
Write units into the fraction: bits cancel bits/s; metres cancel m/s.
  1. d_trans = L/R = 3×10⁶ bits ÷ 1.5×10⁶ bits/s = 2 s.
  2. 3000 km = 3×10⁶ m. d_prop = d/s = 3×10⁶ ÷ 2×10⁸ = 0.015 s = 15 ms.
  3. Nodal delay also includes processing and queueing.
  4. Path throughput = minimum link rate = 1 Mbps.
If doubledd_transd_prop
Packet length L×2unchanged
Rate R÷2unchanged
Distance dunchanged×2

Queueing varies with congestion; processing checks the packet and selects its output link.

Trap Throughput is never the sum of link rates. Improving a non-bottleneck link changes nothing.

20 · Worked: lexical analysis M7 · worked example

if (a == b) answer = 42;

if | ( | a | == | b | ) | answer | = | 42 | ; keyword · bracket · symbol · operator · symbol bracket · symbol · op · number · ; TOTAL = 10 tokens
Longest-match rule keeps == together; spaces do not become tokens.
Token(s)Class
ifkeyword
( and )bracket
a, b, answersymbol / identifier
== and =operators, each one token
42number
;symbol / terminator
  1. Ignore whitespace/comments.
  2. Scan left-to-right, longest token first.
  3. Classify each token; count = 10.
  4. Do not claim lexical analysis proves valid syntax; only parsing does.

Compiler trap table

ClaimVerdict
Comments are tokensNo; scanner discards them

21 · Worked: Round-Robin M8 · worked example

Given: all arrive at 0; A=200 ms, B=100 ms, C=300 ms; quantum=100 ms; queue A,B,C; ignore switching.

quantum = 100 ms · order A B C A C C ABCACC 0100200300400500600
Source redraw: B completes at 200; A at 400; C at 600.
ProcessFinishBurstWait = finish−burst
A400200200 ms
B200100100 ms
C600300300 ms
Answeraverage waiting = (200+100+300)/3 = 600/3 = 200 ms.
  1. Take at most one quantum from queue head.
  2. If unfinished, append to queue tail; if finished, remove.
  3. Read completion times only after the timeline is correct.
  4. For simultaneous arrival, subtract burst from completion.

Trap B finishes after its first slice; do not return it to the queue. C takes consecutive final slices only because nobody else remains.

22 · Scheduling + deadlock checks M8 · topic map

choose the time quantum too smallmore switches too largelonger waits efficiency = slice/(slice+switch) ×100%
The quantum is a responsiveness/overhead trade-off, not a universally maximised value.
Question cueMethod / exact condition
“Runs to completion in arrival order”FCFS
“Fixed time slice, preempt”Round-Robin
Useful-work fractionslice/(slice+switch)
RAG single-unit cycleDeadlock
RAG multi-unit cycleMay deadlock; test whether anyone can finish

Resource-arrow grammar

process → resourceprocess requests / waits
resource → processresource unit allocated / held

State order: CREATE → READY → RUN → FINISH, with RUN↔WAIT when I/O blocks/unblocks. Ready processes can run; waiting processes cannot until their event completes.

23 · Worked: matrix cipher GO → UU M9 · worked example

Given: A=0…Z=25; V=[6 14] for GO; M=[[3,5],[2,3]]; arithmetic mod 26.

GO=[6 14] × 3 52 3 =[46 72] mod 26 → [20 20] 20,20 → UU
Multiply first, reduce each entry modulo 26, then map numbers back to letters.
  1. G=6 and O=14, so V=[6 14].
  2. V·M = [6·3+14·2, 6·5+14·3] = [46,72].
  3. 46 mod 26=20; 72 mod 26=20 → [20,20].
  4. 20=U, so ciphertext=UU. Decrypt with M′: [20 20]·M′ mod 26=[6 14]=GO.
AnswerC = UU; inverse condition M·M′ = I mod 26.

Trap Keep row-vector orientation V·M. Both outputs use both input letters: that diffusion is the point.

24 · Worked: Turing complement M10 · worked example

Rules: (1,0,1,1,R) and (1,1,0,1,R). Start state 1 on leftmost symbol of …b 1 0 1 b….

read 1/write 0/R · read 0/write 1/R 101001011010 next symbol is blank b · no (1,b) rule HALT · output 010
Source redraw: one transition per bit; the missing blank rule is what stops the machine.
StepRead/actionTape fragment after
11→0, R0[0]1
20→1, R01[1]
31→0, R010[b]
4No (1,b) rulehalt; 010
Answer101 → 010, then halt on blank.

Trap Tuple field 3 is the symbol written; field 4 is next state. The head move occurs after the write/state change.

25 · Security fast recall M9 · topic map

PromptAnswer discriminator
Bulk data, speedSymmetric, e.g. AES
Secure key distributionPublic-key / Diffie–Hellman
Authenticate public keyDigital certificate
Preserved letter frequencyCaesar/substitution weakness

26 · Worked: Winograd reasoning M11 · worked example

“The trophy doesn't fit in the suitcase because it is too big.”

  1. Grammar permits trophy or suitcase.
  2. Commonsense says the too-big object fails to fit: “it” = trophy.
  3. Change “big” to “small” and the referent flips to suitcase: meaning, not syntax, resolves it.

Turing test: a text judge cannot reliably distinguish machine from person; this tests behaviour, not mechanism. Neural net: weighted, layered units; forward pass predicts; back-propagation sends error backward to adjust weights. No numeric calculation here.

27 · Method chooser all final modules

What does the prompt give? bits/baseconvert truthSOP L,R / d,sdelays burstsRR line tokens/BNFscan/parse V·M mod26cipher state,symTuring
One cue selects one mechanical procedure. Write the setup before doing arithmetic or tracing.
Write this before workingbinary: fix width · circuit: mark Y=1 rows · machine code: 4|12 fields · network: units · scheduler: queue · cipher: V·M · Turing: state/head.

28 · Final error scan faq + study strategies

Before submittingCommon wrong turn
State bit width and rangeSymmetric two's-complement range
Drop carry beyond fixed widthReport a fifth bit
Bar 0s in SOPBar the 1s
Fetch before decodeScramble PC/MAR/MDR/IR
Keep units visibleMix Mbit, bit, km, m
Tokenise longest matchSplit == or count comments
Timeline before waitingGuess completion times
Cycle rule states resource unitsCall any cycle a deadlock
Matrix orientation + modReverse M·V or forget mapping
Tuple fields 3/4 distinctSwap write and next state

Last pass Mechanical questions reward visible method. Preserve the fixed width, operand order, units, queue order, matrix orientation and head position so a small slip cannot propagate unseen.

Your exam allows one A4 sheet of notes, both sides. Check on the LMS whether printed notes are accepted; if they must be handwritten, copy it.
asksia.ai/cheatsheet/auckland-compsci110 · Full COMPSCI 110 study guide →Forward this to your tutorial group
v2 · 2026-10-16
Semester Two examination period, 29 October – 16 November 2026.
Shared by ________

Want one for YOUR exact syllabus?

Sia is your free desktop study agent. Drop your University of Auckland COMPSCI 110 slides — Sia builds a sheet tailored to YOUR exam. Better than this library because it knows YOUR materials.

↓ Download Sia · Free