COMP30023 · Computer Systems
Memory Management
Week 4 covers how the OS gives each process a private virtual address space: base-and-limit relocation, paging and page tables, virtual-to-physical address translation, the TLB, and page-replacement policies. Computing a physical address from a page table, splitting an address into page-number and offset, and explaining whether a TLB is necessary are staple mid-semester-test and exam items.
What this chapter covers
- 01Why memory management: multiprogramming, isolation/security, and running processes larger than physical RAM
- 02Base-and-limit registers (dynamic relocation): check logical address < limit, then physical = logical + base
- 03Contiguous allocation, the free-hole list, first-fit / best-fit / worst-fit, and external fragmentation
- 04Paging: fixed-size pages and frames, the per-process page table and the Page Table Base Register (PTBR)
- 05Address translation: page number (top bits) + offset (bottom bits); physical = frame × frame size + offset
- 06Page-table entry bits (present/absent, referenced R, modified/dirty M); internal fragmentation and page-size trade-offs
- 07Page faults and page-replacement algorithms: Optimal, FIFO, Second-Chance, LRU and Aging
- 08The Translation Lookaside Buffer (TLB): an associative cache of page-table entries; hit/miss and flush on context switch
Virtual-to-physical address translation with a page table
- +1Split the logical address into a page number and an offset using the page size 1024. Page number = 5000 ÷ 1024 = 4 (since 4 × 1024 = 4096 ≤ 5000 < 5120), and offset = 5000 − 4096 = 904.
- +1Look up page 4 in the page table: page 4 → frame 6.
- +1Physical address = frame number × frame size + offset = 6 × 1024 + 904 = 6144 + 904 = 7048.
- +1Only the page-number field is translated (page 4 → frame 6); the offset 904 is copied through unchanged, because a page and its frame are the same size, so the position within them is identical. Physical address = 7048.
Key terms
- Paging
- Dividing a process's virtual address space into fixed-size pages and physical memory into equal-size frames. Pages map to frames via a page table, need not be contiguous, and need not all be resident — some can live on disk.
- Page table
- A per-process table (pointed to by the Page Table Base Register) mapping each virtual page number to a physical frame number, plus control bits. It is indexed by the page-number part of a virtual address.
- Address translation (paging)
- A virtual address splits into a page number (top bits) and an offset (bottom bits). Physical address = frame number × frame size + offset, where the frame comes from the page table and the offset is copied unchanged.
- Base and limit registers
- A simpler scheme: a process occupies one contiguous region delimited by a base (start) and limit (length). The MMU checks logical address < limit, else traps, then computes physical = logical + base.
- Page fault
- The MMU traps when a referenced page's present/absent bit is 0 (not in memory). The OS selects a victim frame (writing it back if its modified bit is set), loads the needed page from disk, updates the page table, and restarts the faulting instruction.
- Translation Lookaside Buffer (TLB)
- A small associative hardware cache in the MMU holding recently used page-table entries, searched in parallel. A hit builds the physical address without a second memory access; a miss walks the page table. It is typically flushed on a context switch, since page-to-frame mappings are per-process.
Memory Management FAQ
How do I convert a virtual address to a physical address under paging?
Split the virtual address into a page number and an offset using the page size: page number = address ÷ page size, offset = address mod page size. Look up the page number in the page table to get the frame number. Then physical address = frame number × page size + offset. The offset is always copied through unchanged; only the page number is translated. If the page size is a power of two, the offset is just the low log2(page size) bits.
Is a TLB necessary for address translation?
No — the page table alone is enough to translate every address, so a TLB is not strictly required. But without it every memory reference needs two memory accesses (one to read the page table, one for the data), which roughly halves memory throughput. The TLB is an associative cache of recent page-table entries that turns most translations into a single fast lookup, so it is a large speed-up rather than a correctness requirement. This 'necessary vs helpful' distinction is a classic exam question.
What is the difference between internal and external fragmentation?
Internal fragmentation is wasted space inside an allocated unit: with fixed-size pages, a 13-byte process using 4-byte pages needs four pages (16 bytes), wasting 3 bytes on the last page. External fragmentation is wasted space between allocations: with contiguous (base/limit) allocation, enough total free memory exists but it is split into non-contiguous holes, so a request cannot be satisfied. Paging removes external fragmentation but introduces internal fragmentation.
What do the R and M bits in a page-table entry do?
The referenced bit (R) is set by the MMU whenever the page is accessed, and the modified/dirty bit (M) is set whenever it is written. Replacement algorithms use them: Second-Chance skips a page whose R bit is set (clearing it and giving a second chance), and on eviction a page whose M bit is set must be written back to disk while a clean page can simply be discarded. Aging shifts the R bit into a per-page counter each clock tick.
Can AI help me with memory management in COMP30023?
Yes. Sia can generate fresh paging problems, check your page-number/offset split and physical-address arithmetic, and walk through page-replacement traces (FIFO, Second-Chance, LRU, Aging) or first/best/worst-fit hole selection step by step. It is a study aid for learning the method and rehearsing; it does not do your graded MST, exam, quizzes or projects, and University of Melbourne academic-integrity rules apply.
Exam move
Memory management contributes both conceptual and numeric marks and is examined in the mid-semester test as well as the final, so split your practice between the two. On the numeric side, drill address translation until it is automatic — page = address ÷ page size, offset = remainder, physical = frame × page size + offset — and rehearse the bit-width version (offset bits = log2 page size) since the exam has no calculator and favours powers of two. On the conceptual side, memorise the page-replacement algorithms and be able to run a short FIFO/Second-Chance/LRU trace, explain internal vs external fragmentation, and answer the 'is a TLB necessary' question (no, but it avoids the second memory access). Keep the R/M bit roles and the page-fault handling sequence at your fingertips. This topic recurs in tutorials and underpins later systems reasoning, so steady work protects your WAM; confirm the MST and exam dates on Canvas.
Working through Memory Management in COMP30023? Sia is AskSia’s AI Computer Science tutor — ask any COMP30023 Memory Management question and get a clear, step-by-step explanation grounded in how COMP30023 is taught and assessed. Read this chapter free, then take your hardest questions to Sia.
