COMPSCI110 · Introduction to Computer Systems
Computer Organisation
Module 3 of University of Auckland COMPSCI110 assembles the gates of Module 2 into a whole machine — the von Neumann model. You learn its stored-program idea and four subsystems (Memory, I/O, ALU, Control Unit), how the ALU and registers form a datapath, how the control unit's special registers (PC, IR, MAR, MDR) drive the fetch–decode–execute cycle, and how RAM and its address decoder are organised. It carries 3 marks on the final exam and is the bridge that makes Module 4 assembly make sense.
What this chapter covers
- 01The von Neumann model: stored-program concept (instructions and data share one memory), four subsystems (Memory, I/O, ALU, Control Unit = CPU is ALU+CU), sequential execution and the 'von Neumann bottleneck'
- 02The ALU: arithmetic, comparison and logic operations, working registers, and the datapath (registers → circuits → registers); selecting an operation with a decoder or (in practice) a multiplexor
- 03Instruction format [opcode][address field(s)] and bit-width sizing: opcode bits, operand/register bits from the register-file size
- 04Control-unit registers: PC (next instruction address), IR (current instruction), and the clock alternating 0/1 to settle circuits then update state
- 05Memory: RAM/ROM, cell (byte) addressing, maximum memory = 2ᴺ for an N-bit address, and the MAR/MDR pair for fetch (non-destructive) and store (destructive)
- 06The address decoder and 2-D (row/column) memory that cuts decoder lines from 2ᴺ to 2×2^(N/2)
- 07The memory hierarchy (registers → L1/L2/L3 cache → RAM → SSD/HDD), the principle of locality and cache hit rate; RISC vs CISC instruction sets
Sizing an instruction: opcode, operand and register bits
- +1Opcode width: 16 distinct instructions need 16 distinct codes, and 2⁴ = 16, so the opcode is 4 bits.
- +1Operand bits: the instruction register holds 16 bits and the opcode uses 4, leaving 16 − 4 = 12 bits for the address/operand fields.
- +1Register field: 16 registers likewise need 2⁴ = 16 codes, so addressing one register takes 4 bits.
- +1Fit check: OPCODE REG1 REG2 REG3 = 4 + 4 + 4 + 4 = 16 bits, exactly filling the instruction register. So the three-register format fits perfectly.
Key terms
- Stored-program concept
- The defining von Neumann idea: program instructions and data live in the same memory and are addressed the same way. It makes a machine general-purpose (load a different program to do a different job) but forces instructions and data to travel the same bus — the source of the sequential 'von Neumann bottleneck'.
- ALU & datapath
- The Arithmetic-Logic Unit performs arithmetic (+, −, ×, ÷), comparison (=, <, >) and logic (AND, OR, NOT). The datapath is the wiring registers → circuits → registers along which operands flow; more registers let the machine hold intermediate results of a compound expression.
- Control unit
- The subsystem that sequences execution: it fetches each instruction, decodes the opcode and issues the control signals that carry it out. It is itself a sequential (state-machine) circuit, driven by a clock that alternates 0 (let circuits settle) and 1 (allow state to change).
- MAR / MDR
- The two registers that connect the CPU to memory: the Memory Address Register holds the address being accessed, and the (two-way) Memory Data Register holds the data being fetched from or stored to that address. A fetch is non-destructive (memory keeps its value); a store is destructive (it overwrites).
- Address decoder & 2ᴺ rule
- An N-bit address can select one of 2ᴺ memory cells, so maximum memory size = 2ᴺ cells. A decoder turns the N-bit address into a single selected line; organising memory as a 2-D row/column grid cuts the decoder lines from 2ᴺ to 2 × 2^(N/2).
- Cache & memory hierarchy
- Levels ordered by speed and cost: registers → L1/L2/L3 cache → main RAM → SSD/HDD → archival. Cache is small, fast and near the CPU; it works because of the principle of locality (recently/nearby-used data is likely to be reused). Cache hit rate is the fraction of accesses served from cache.
Computer Organisation FAQ
What are the four subsystems of the von Neumann model?
Memory (stores both instructions and data), Input/Output (moves data in and out), the Arithmetic-Logic Unit (does the computing) and the Control Unit (sequences everything). The ALU and Control Unit together are what we call the CPU. The model's other two defining features are the stored-program concept and sequential execution of instructions.
What's the difference between the MAR and the MDR?
The MAR (Memory Address Register) holds the address you want to access — the 'where'. The MDR (Memory Data Register) holds the data itself — the 'what'. To fetch, you put the address in the MAR, trigger a read, and the cell's contents arrive in the MDR. To store, you load both the MAR (address) and MDR (value), then trigger a write. The MDR is two-way; the MAR is one-way (address out).
Can AI help me with computer organisation in COMPSCI110?
Yes, as a study aid. Sia can walk the fetch–decode–execute steps in order, size an instruction's opcode/operand/register fields for you to check, explain why 2-D memory saves decoder lines, and quiz you on the register roles (PC, IR, MAR, MDR). Use it to build understanding and rehearse — it explains and checks but does not do graded work or the exam for you, and academic-integrity rules apply to controlled assessments.
What is the von Neumann bottleneck?
Because instructions and data share one memory and one path to the CPU, the machine must move them sequentially over that single channel — so the CPU often waits on memory rather than the other way round. That serial instruction-and-data traffic is the 'von Neumann bottleneck', and much of modern architecture (caches, pipelining, wider buses) exists to work around it.
How much memory can an N-bit address reach?
Exactly 2ᴺ cells, because N bits give 2ᴺ distinct addresses. So a 16-bit address reaches 2¹⁶ = 65,536 cells (64 KB with byte cells), a 20-bit address reaches 1 MB, and a 32-bit address reaches 2³² = 4 GB. This 2ᴺ rule is the same counting idea that sizes opcode and register fields — bits determine how many distinct things you can name.
Exam move
Anchor this module on one diagram you can redraw from memory: the four subsystems, the CPU (ALU + Control Unit) inside, and the PC/IR/MAR/MDR registers wired to memory. Learn the fetch cycle as a fixed four-step sequence in exact order — PC→MAR, FETCH (cell→MDR), MDR→IR, PC+1 — because the order is examinable and easy to scramble. Drill the bit-counting rule until it's automatic (k distinct things → ⌈log₂ k⌉ bits; 2ᵇ things → b bits) and practise sizing opcode, operand and register fields, keeping register-count and memory-size questions separate. Keep the 2ᴺ memory rule and a couple of worked sizes (N=16 → 64 KB, N=32 → 4 GB) on your sheet. Understand the MAR/MDR roles and the non-destructive-fetch vs destructive-store distinction, and be able to name the memory hierarchy top to bottom with the locality idea behind caching. This module is only 3 marks, but it is the mental model Module 4 assumes.
Working through Computer Organisation in COMPSCI 110? Sia is AskSia’s AI Computer Science tutor — ask any COMPSCI 110 Computer Organisation question and get a clear, step-by-step explanation grounded in how COMPSCI 110 is taught and assessed. Read this chapter free, then take your hardest questions to Sia.
