Can I bring notes into the ELEC1601 final exam?

The ELEC1601 course materials this cheatsheet was built from do not confirm the permitted materials for this semester's final exam at University of Sydney. Check the exam instructions on the LMS before the exam; use this sheet to revise and self-test.

How much is the ELEC1601 final exam worth?

The final exam is worth 35%. It is a two-hour mandatory written exam, AI is prohibited, and it is a hurdle task.

What does the ELEC1601 final reward?

It rewards a coherent model across binary representation, registers, memory addresses, stack state and control flow, with explanations that connect bits, instructions, state and observable behaviour.

How should a fixed-width signed value be interpreted?

State the width and representation first. A bit pattern has no signed or unsigned meaning until both are specified.

What is the core state-trace method?

Record register, memory, flag and control-flow changes after each relevant machine operation, then test ordinary, boundary and invalid cases.

What must a subroutine trace prove?

It must show that arguments, results, the return address and all state assigned to the caller or callee survive the call correctly.

ELEC1601 Cheatsheet · Introduction to Computer Systems · USyd

ELEC1601

Introduction to Computer Systems

School of Electrical and Computer Engineering · USyd · EXAM REVISION SHEET

Full guide + ask Sia about ELEC1601

SIDE 1/2 DEFINITIONS · FORMULAS · DECISION RULES · MACHINE-STATE CHECKSSemester 2 · 2026v2 · 2026-10-25

0 · Exam Mapcourse.json · brief

FQ 20XQ 10Lab 15Att 0EP 10XP 5AP 5FINAL 35

Permitted materials: not confirmed for this offering in the course materials we hold — check the exam instructions on the LMS.

Assessment	Wt	Control
Fundamentals Quizzes	20%	4 in-person · hurdle
Extension Quizzes	10%	3 in-person
Essential Lab Completion	15%	group + individual explanation · hurdle
Laboratory Attendance	0%	participation · hurdle
Essential / Extension / Advanced Project	10 / 5 / 5%	Essential is hurdle
Final exam	35%	2-hour written · AI prohibited · hurdle

The mandatory section uses multiple-choice questions based on in-semester tests; the advanced section carries a threshold for extra marks. All essential assessments must be passed, and lab participation is compulsory, to pass.

Course-wide answer route: represent → trace → connect → test.

Source-derived state control: every arrow must be a checkable transition.

1 · State-Trace MethodC1 · overview

Program state is the complete set of variable, register, memory, flag and control-position values at one instant. Record only state that can be read, changed or depended upon.

Step	Write	Check
Before	width/representation; PC/control point; registers; relevant memory; flags	preconditions explicit?
Execute	instruction/operation and operands	what is read; what is written?
After	new register, memory, flag and control state	next branch/call/iteration?
Test	ordinary · boundary · invalid	one rule isolated?

Exam check Explain why the result follows. A correct output without the state transition is not a complete machine-level explanation.

2 · Binary, Hex & SignedC3 · glossary/faq

Positional binary: each bit contributes a power of two. Hexadecimal: one digit 0–9/A–F compactly represents four bits. Preserve the fixed width while converting.

representation rulebit pattern + width + interpretation → machine meaning
negative two's-complement: invert every bit, then add one

Source-derived conversion route: never detach bits from width and representation.

Question cue	Do	Say
binary ↔ hex	keep leading zeros; group into nibbles	same pattern, new notation
negative integer	write positive at stated width → invert → +1	two's-complement interpretation
same bits, two values	apply signed and unsigned interpretations separately	bits did not change
overflow	trace the fixed-width operation	state width before judgement

A bit pattern has no signed or unsigned meaning until the representation and width are specified.

For a full-credit conversion, label the source representation, keep leading zeros required by the width, show the intermediate pattern, then label the target notation and interpretation. To test overflow, inspect the result at the same fixed width; do not silently expand the representation or discard a carry without stating what the chosen width does.

Same stored pattern; interpretation selects the value.

2b · Signed-Byte Checkcourse worked example

+18 = 00010010
invert = 11101101
add 1 = 11101110 = 0xEE
signed: −18 · unsigned: 238

3 · Fixed vs Floating PointC4 · glossary/faq

Representation	Structure	What to check
Fixed-point	integer pattern + agreed scale locating the radix point	resolution, rounding, representable limits
Floating-point	sign + exponent + significand	field meaning, precision spacing, range

fixed-point meaningrepresented value = stored integer pattern interpreted with the agreed fixed scale

floating-point reading ordersign → exponent → significand → represented magnitude

Source-derived encoding route: format choice controls later checks.

Decision rules

If the task fixes a radix-point position, treat the pattern as fixed-point and keep the scale visible throughout.
If the task separates sign, exponent and significand, decode those floating-point fields before comparing values.
If the task asks “more range?”, do not infer “more precision”. These are different properties.
If a decimal appears, allow for the fact that it may not have an exact finite binary encoding.

Exam check More range does not guarantee more precision. State the representation consequence—rounding, overflow or comparison—not merely the field names.

Precision concerns spacing; range concerns reachable magnitudes.

3b · Encoding Answer FrameC4 · worked method

Fix the value, width and chosen representation.
Write the scale or the sign/exponent/significand field roles.
Carry the encoding through without changing conventions.

4 · AVR Instruction TraceC5 · glossary/faq

Mnemonic names the operation; register operands are the locations read or written; status flags record conditions such as zero, carry, negative or overflow.

Source-derived AVR trace: operation → operands → result → flags/control.

Trace column	Question it answers
PC / control	which instruction executes next?
mnemonic	what operation is named?
source operands	which registers/locations are read?
destination	which register/location changes?
flags	what arithmetic condition is now recorded?

An assembly sequence is correct only under the stated register contents, data width and calling assumptions.

5 · CPU & Memory CycleC6 · topic/faq

Source-derived architecture link: encoding reaches visible state through fetch/decode/execute.

Object	Role	Do not confuse
CPU datapath	moves/transforms data during execution	not the whole processor design
register file	fast operands, addresses, intermediate values	not general data memory
program memory	executable instructions	not mutable program data
data memory	mutable values	not instruction encoding
instruction encoding	supplies operation and operand information for fetch/decode	not the visible result
visible machine state	register, memory, flag and control changes after execution	not unstated timing detail

Limit A simplified architecture diagram omits timing and implementation detail; use it to explain state, not as a complete processor design.

6 · Addressing ModesC7 · glossary/faq

Byte address identifies one byte-sized storage unit. Pointer register stores an address used for indirect access and may be updated.

Source-derived object map: pointer ≠ address ≠ value at that address.

Mode	Location comes from	Trace
direct	location named explicitly	named address → value
indirect	pointer register	pointer value → address → value
indirect + update	pointer register, then modified	accessed location and pointer after access

address tracepointer before → effective byte address → value read/written → pointer after

Never write “the pointer contains the data” when it contains the address. A later access may change solely because the pointer changed.

7 · Runtime StackC8 · glossary/faq

Source-derived stack model: one call's return information, saved state and locals.

Event	Prove
push	value stored and stack pointer moves under the stated AVR convention
pop	value retrieved and matching pointer change
nested call	each activation record and return information remain distinct
return	caller state and continuation are recovered

Join the memory and stack traces: record the byte address touched, the value stored or retrieved, the stack pointer before and after, the activation record owning that slot, and the control position restored on return. If any one is missing, later nested-call state cannot be proved.

Limit Stack growth direction and exact call behaviour are architecture-specific; follow the course's AVR convention.

8 · Calls & ConventionsC9 · glossary/faq

Source-derived call contract: arguments, continuation, preservation, result.

Responsibility	Question
parameter passing	which inputs or addresses cross the interface?
caller-saved	what must the caller preserve before calling?
callee-saved	what must the subroutine restore before returning?
result	where is the output and who may overwrite it?

A function can return the right sample result yet violate the calling convention and corrupt later execution.

9 · Branches & LoopsC10 · glossary/faq

Source-derived loop proof: relevant flags drive branch; invariant + progress establish correctness.

operation/comparison → condition flags → branch instruction → body update → re-test

A loop invariant remains true before and after every iteration. Show it initially, show the body preserves it, then connect loop exit to the required result and boundary behaviour.

Interpret a branch only from flags produced by the immediately relevant comparison or arithmetic operation.

10 · Polling & InterruptsC2 glossary/faq

If the cue is…	Trace this	Boundary
polling loop	read status → branch → repeat/service	software repeatedly checks
interrupt response	event → handler → shared state → resume	timing/handler duties controlled

Remember An interrupt improves responsiveness only when shared state, timing and handler responsibilities are controlled.

ELEC1601

Self-Test Drills · Answer Paths · Classic Traps

Introduction to Computer Systems · USyd · EXAM REVISION SHEET

Full guide + ask Sia about ELEC1601

SIDE 2/2 FIVE WORKED DRILLS · IF-X-THEN-Y CARDS · FAST RECALL · EXAM-MORNING PLANSelf-test before reading answersv2 · 2026-10-25

11 · Method Choosertopic maps · faq

Source-derived chooser: identify the changing object before choosing a method.

If you see…	Do this
bit pattern	state width + representation; convert without dropping bits
fixed/float value	state scale or fields; check precision/range
assembly sequence	trace operands, destination, flags and next control
pointer/address	separate pointer, address and stored value
call/return	track arguments, saved state, result, return information
branch/loop	find producing flags; show invariant and termination
input event	choose polling or interrupt trace; expose shared state/timing

12 · Worked 1 · Signed Bytecourse worked · 4 marks

Q. Represent −18 as an 8-bit two's-complement value, convert it to hexadecimal and explain why the same bits can mean 238.

Complete number path from the source example; every intermediate pattern retained.

1: +18 = 00010010.
1: invert → 11101101; add one → 11101110.
1: group nibbles → 1110 1110 = 0xEE.
1: signed 8-bit meaning = −18; unsigned meaning = 238.

Self-mark: award nothing for a bare 0xEE if the width, inversion, addition and signed/unsigned interpretation are absent. Cover the answer, reproduce all three patterns, then explain in one sentence how identical bits support two meanings.

Trap Do not attach signed meaning until width and representation are explicit.

13 · Worked 2 · Polling / InterruptC2 worked · 4 marks

Task. Trace when a microcontroller reads an input and changes an output under polling and interrupt designs.

Source-derived comparison: repeated software check versus event-triggered handler.

1: mark the complete program state before input service.
1: polling: show read, decision, repeat/service; interrupt: show event, handler entry and responsibilities.
1: trace shared-state and output changes, then the next control position.
1: qualify: improved responsiveness depends on controlled shared state, timing and handler duties.

Trace row	Polling	Interrupt
trigger	software check	hardware event
between events	loop keeps checking	other work may run
proof burden	read/branch/repeat	entry/shared state/resume

13b · State-Trace Drill CardC1 · C2

Step	PC/control	registers	memory	flags/output
before	____	____	____	____
read	____	____	____	____
decide	____	____	____	____
service	____	____	____	____
after	____	____	____	____

Before executing, predict the output for ordinary, boundary and invalid inputs. Change one condition at a time; otherwise the failed rule cannot be localised. For an interrupt trace, identify which state is shared, who may change it, what the handler must finish, and where normal execution resumes. For polling, show the repeated read and the exact decision that exits or services the loop.

Practice loop: retrieve → transfer → counter-case → revise.

Fix Define program state before service: variables, registers, memory, flags and control position. In polling, name the repeated check; in interrupts, name handler entry, shared-state change and the resume point.

14 · Worked 3 · AVR TraceC5 worked · 4 marks

Task. Translate a small operation into AVR instructions and trace each register and flag change.

1: name the required operation and starting register contents.
1: state each mnemonic and which register operands it reads/writes.
1: after every instruction, record changed registers and status flags.
1: state the next control action; retain width and calling assumptions.

Source-derived answer grid: never skip the initial state or flag-producing step.

Trap A familiar mnemonic does not prove correctness. Match its operation, operands, width, flags and calling assumptions to the task.

14b · Architecture DrillC6 worked

Source-derived path for connecting instruction encoding to machine state.

Prompt	Answer move
“where is instruction?”	program memory
“where are operands?”	register file and/or data memory, as stated
“what transforms them?”	CPU datapath during execute
“what can we observe?”	register, memory, flag and control changes

Boundary: the diagram is a reasoning aid; it omits timing and implementation detail.

Worked check Start from given register contents and width. For each instruction, write its operation, operands read/written, resulting register state and new zero, carry, negative or overflow flag. Then state next control. If a row fails, repair the first unsupported transition; never infer later state from a familiar mnemonic.

15 · Worked 4 · Address / StackC7–C8 worked · 4 marks

Task. Calculate an accessed location, show pointer updates, then trace nested-call stack state and return information.

Source-derived address calculation: pointer before and after bracket the access.

1: define the pointer register and the byte address it holds.
1: distinguish direct location naming from indirect pointer use.
1: state effective address, value read/written and pointer after.
1: qualify: pointer, address and stored value are different objects.

Source-derived nested-call check: frames and return information must not blur together.

SP before → call/push effect → callee frame → nested effect → return/pop effect → SP after

15b · Stack / Call TrapsC8–C9 faq

Tempting claim	Repair
“stack always grows this way”	state the AVR convention used
“result correct, function correct”	also prove preserved state and return
“pop undoes any push”	match order, value and pointer state
“address equals contents”	write pointer → address → value

15c · Representation TrapsC3–C6 limits

Trap	Repair sentence
bits “are negative”	At the stated width, under two's-complement interpretation…
hex changed the value	Hex is compact notation for the same grouped bits.
range = precision	Range controls magnitudes; precision controls spacing.
mnemonic alone proves result	Trace operands, destination and flags from stated contents.
diagram is complete CPU	It omits timing and implementation detail.

16 · Worked 5 · Branch / CompilerC10–C11 worked · 4 marks

Task. Relate a structured loop or C-level construct to AVR assembly and justify an optimisation safely.

Source-derived optimisation test: compare behaviour, not surface instruction count.

1: define the source construct's required observable behaviour.
1: map operations and control structures to assembly instructions.
1: trace registers, memory, flags and branches through normal and boundary cases.
1: accept the change only if behaviour remains equivalent under the stated assumptions.

Source-derived loop proof: invariant and progress are separate obligations.

Shorter is not automatically correct or faster. Different instruction sequences may be semantically equivalent; show the conditions under which they are.

16b · Branch Judgement CardsC10 faq

If you see X	Do Y
branch mnemonic	name the flag condition and its producer
loop boundary	trace zero/one/final iteration behaviour
non-termination	inspect update, branch polarity and progress
optimised loop	compare observable state on same cases

16c · Sensor–Actuator LinkC12 glossary

Source-derived control cycle: observable action must connect back to bit- and instruction-level state.

17 · Classic Control Trapschapter limits

Trap	Repair sentence
pointer = value	The register holds an address; memory at that address holds the value.
sample output proves call	Also prove calling-convention preservation and return.
branch read in isolation	Use flags from the immediately relevant operation.
shorter = optimised	First prove equivalent observable behaviour.
interrupt always better	Only when shared state, timing and handler duties are controlled.

18 · Fast Recallcourse glossary

Term	Recite
AVR assembly	symbolic mnemonics encoding AVR operations
computer architecture	programmer-visible instruction set, registers, memory model, data paths
stack pointer	register identifying current top boundary of runtime stack
subroutine	reusable sequence entered by call, completed by return
activation record	one call's saved state, locals and return information
loop invariant	property true before and after every iteration
explainable evidence	trace, test and design records that justify system behaviour

Source-derived final review control: object → mechanism → boundary → requested conclusion.

19 · Exam-Morning Plancourse strategy · brief

Retrieve: say the definitions of width/representation, state, pointer, stack pointer, flags, invariant and semantic equivalence without notes.
Trace: complete one blank table across bits → instruction → register/memory/flags → control flow.
Transfer: change one condition and predict the new state before checking.
Counter-case: test ordinary, boundary and invalid inputs; repair the first failed reasoning move.
Verify operations: check the current LMS instructions and exact timetable published by the Exams Office.

answer rhythmdefine object → state rule → show transition → name visible consequence → state boundary