FIT1047 Chap.5 Computer Architecture and CPU Execution
Computer Architecture and CPU Execution
Computer architecture defines the programmer-visible contract of instructions, registers, data forms and addressing, while microarchitecture describes an internal implementation. This chapter follows stored-program instructions through CPU, memory and I/O components.
It distinguishes address, contents and control direction; explains specialised registers and the program counter; and decomposes execution into fetch, decode and architectural state change. Datapath routes move or transform values while control selects sources, operations and state updates. Branches replace normal program-counter sequencing only when their condition or instruction semantics require it.
Every trace names old state, micro-operation, new state and unchanged locations. Because later weekly pages publish outcome scope rather than a detailed readable worksheet, examples are original standard canon and do not predict Demonstration structure. The method prepares students to explain process and memory rather than merely recite component names.
The diagnostic question at every step is which architectural state is permitted to change and which evidence explains that change. Program-counter contents, fetched instruction, operand address and operand contents must remain separate.
The published A2 evidence establishes only a Demonstration purpose around MARIE analysis or writing and explanation of program, process and memory concepts; it does not establish the live format, duration, rubric, trace layout or permitted materials.
What this chapter covers
- 01
Architecture versus microarchitecture
- 02
Stored programs and memory words
- 03
CPU, memory, I/O and interconnect
- 04
Registers and program counter
- 05
Fetch–decode–execute cycle
- 06
Datapath, selectors and control
- 07
Branches, loops and control-flow graphs
- 08
State tables and invariants
- 09
Architectural mutation ledgers
- 10
Separating instruction and operand addresses
- 11
Reconciling control-flow edges with final state
AskSia-authored practice weighting (not an official mark scheme): Fresh load–add–store trace
- fetchFetch address 30, advance normal sequence and decode Load 90.
- loadRead memory[90]=11 into the accumulator.
- addFetch/decode Add 91 and update the accumulator to 19.
- storeFetch/decode Store 92 and write 19 to memory[92].
- checkVerify operands remain unchanged, accumulator remains 19 and normal PC continuation follows.
Key terms
- Instruction-set architecture
- The visible contract of operations, registers, data and addressing provided to software.
- Microarchitecture
- A specific internal datapath/control implementation of an instruction-set architecture.
- Program counter
- A register identifying the next instruction address under current control flow.
- Instruction register
- Storage holding the current fetched instruction word for decode.
- Datapath
- Registers, ALU, buses and selectors that move or transform values.
- Control unit
- Logic that decodes instructions and selects datapath operations and state updates.
- Architectural state
- Programmer-visible information whose value can affect later execution, such as registers and memory. A trace should identify which instruction changes each state element and should not invent microarchitectural timing details that are outside the stated model.
- Mutation ledger
- A list of the state elements each instruction is allowed to read or write. Comparing it with a completed trace exposes unexplained changes, missing effects and confusion between an address and the contents stored at that address.
Computer Architecture and CPU Execution FAQ
Is an address the same as the stored contents?
No. An address selects a location; a memory read returns the contents stored there. Keep them in separate trace columns.
Does fetch execute the instruction?
Fetch obtains instruction bits and prepares normal sequencing. Decode interprets fields; execute performs the architectural operation.
Why does a branch not always jump?
A conditional branch selects a target only when its tested condition holds. Otherwise the incremented normal continuation remains.
What is the difference between datapath and control?
The datapath contains possible value routes and operations; control chooses which source, operation and write-enable apply for the decoded instruction.
How can a final trace be checked?
Use representation checks, value-dependency order, instruction mutation patterns, control-flow reachability and algorithm invariants. Every final difference should have one justified cause.
Why should unchanged state be recorded in a CPU trace?
Explicitly preserving unaffected registers and memory prevents accidental writes from disappearing inside a final snapshot. It also proves that control and write-enable decisions were understood, not merely that the changed values happened to be correct.
What is safely known about the FIT1047 Demonstration?
The published purpose covers MARIE analysis or writing and explanation of program, process and memory concepts. The current evidence does not establish exact structure, duration, rubric, simulator steps or permitted materials, so those must be taken from current Moodle instructions.
Assessment move
Draw three aligned views: system block diagram, control-flow graph and state table. Label every arrow as address, data or control. For each fresh instruction sequence, record PC before fetch, instruction word, decoded operation/address, operands, register changes, memory changes and next PC. Mark values that must remain unchanged. Use selectors and write-enables to explain why a value on a wire does or does not enter storage.
Test branches with one value for each outcome and one boundary value. For loops, state an invariant and progress measure before tracing. Distinguish architectural claims from implementation choices such as exact cycles or caches unless those details are explicitly supplied. Add an architectural-effect ledger listing exactly which register or memory location each instruction may change.
After a trace, reconcile every final difference with one ledger entry and every expected effect with a trace row. Draw PC as a register containing an address, memory at that address as a separate cell and the fetched word entering the instruction register.
This picture eliminates the claim that the processor “executes the number in PC.” For datapath practice, draw all candidate sources into a selector, name the decoded control and show that unselected values cannot be captured without write-enable. Build one loop graph with normal, taken and exit edges, then test values taking each edge.
Finally, explain the same sequence at two scopes: architectural results and conceptual register transfers. Do not add pipeline stages, cache hits or precise cycle counts unless an implementation explicitly supplies them. Treat the course-developed textbook as support for architecture vocabulary and conceptual scope only.
Rebuild every diagram and trace in your own notation, and do not copy its prose, register-transfer sequence, figures or worked solutions. Confirm all A2 logistics directly in current Moodle.
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