FIT1047 Chap.4 Gates, Circuits, K-Maps and Logisim
Gates, Circuits, K-Maps and Logisim
A gate circuit is an implementation of a Boolean function with signal direction, intermediate nodes and physical or simulated timing. This chapter translates expressions into networks from the deepest subexpression outward, then reads networks back into fully parenthesised expressions. Truth tables remain the stable functional contract.
Karnaugh maps arrange rows in Gray-code adjacency so valid power-of-two groups remove variables that change within a group; wrap-around and overlap are allowed when semantically valid. Simulation is treated as an engineering process: label pins and nodes, build incrementally, record expected/observed values for every row, trace the first differing node, repair, then rerun the whole table.
Stable truth-table correctness is distinguished from transition glitches and propagation delay. The detailed Written specification requires circuit reasoning, testing and reflection and prohibits generative-AI-produced assessment content, so this guide intentionally uses different functions and provides method rather than task completion.
Functional correctness, implementation structure and transition behaviour are separate claims. A complete stable truth table verifies the Boolean mapping; labelled intermediate nodes support localisation; propagation observations concern timing rather than a new logical function. K-map groups must be justified by adjacency and stable literals, then checked by reconstructing the output rows.
The published A1 detail supports circuit testing and reflection as skills, but the live personalised circuit, screenshots and reflection must be completed independently.
What this chapter covers
- 01
Gate truth functions and signal direction
- 02
Expression-to-circuit translation
- 03
Circuit-to-expression reading
- 04
Combinational state and propagation
- 05
Gray-code K-map placement
- 06
Valid groups and stable literals
- 07
Incremental simulator construction
- 08
Exhaustive testing and technical reflection
- 09
Reconstructing a truth table from a simplified circuit
- 10
First-divergent-node debugging
- 11
Separating stable logic from transition observations
AskSia-authored practice weighting (not an official mark scheme): Fresh K-map simplification
- placePlace ones in the four identified cells using Gray-code labels.
- groupForm one four-cell group; A changes and C changes while B remains zero.
- termRetain the stable-zero variable as NOT B.
- circuitImplement with one inversion of B under the assumed gate library.
- verifyReconstruct all eight rows from NOT B and compare with the source list.
Key terms
- Fan-in
- The number of inputs accepted by a gate under the chosen implementation library.
- Fan-out
- The number of destinations driven by one signal under the design.
- Karnaugh map
- A Gray-code arrangement of truth-table cells used to identify adjacent implicants.
- Implicant
- A product term covering one or more output-one assignments.
- Propagation delay
- Time between an input change and the resulting stable output change.
- Junction
- An explicit electrical/logical connection where wires meet in a circuit diagram.
- Functional contract
- The complete stable input-to-output mapping a circuit must implement. Expressions, K-map groups, schematics and simulator builds are alternative representations of this contract and should be checked against it rather than against visual neatness.
- First divergent node
- The earliest labelled internal signal whose observed value differs from the value predicted by the expression tree for a fixed input. Finding it narrows the fault to the preceding logic or connection and avoids random rewiring.
Gates, Circuits, K-Maps and Logisim FAQ
Why must a K-map group have power-of-two size?
Each doubling pairs terms differing in one variable, allowing that changing variable and its complement to disappear.
Can groups overlap or wrap?
Yes. Edges are adjacent under Gray code, and overlap can support larger or essential coverage. Diagonal cells are not adjacent.
Why use intermediate node labels?
They become truth-table columns and simulator probes, allowing a failing row to be traced to the first local mismatch.
Does exhaustive row testing prove timing safety?
It proves stable combinational mapping for the tested model. Transition order and propagation delay require separate dynamic observations.
How should reflection be written?
Explain initial model, observed mismatch, diagnosis, change and complete retest. Keep claims proportional to the simulator evidence and write the live reflection independently.
Why does exhaustive stable-row testing not settle propagation behaviour?
Truth-table rows describe settled input combinations. During a transition, different paths can settle at different times and briefly produce another output. Timing observations must therefore be recorded separately from stable functional correctness.
How can K-map simplification be independently verified?
Translate every selected group into its stable literals, form the simplified expression and regenerate the complete output column. Compare that column row by row with the original table, including zeros that must remain uncovered.
Assessment move
Choose a fresh expression, draw its tree and give every intermediate result a node name. Build the circuit in dependency order and read it back to an expression before simulation. For K-maps, transfer rows one by one, tick every source row, mark legal groups, list stable variables and reconstruct the table from the simplified answer.
In the simulator, test each subcircuit during construction, then exhaustively test the completed function. Record input, expected output, observed output and first differing node. Add transition tests only after stable rows pass. Retain an incorrect version and annotate the exact repair; this develops stronger reflection than a polished screenshot.
Do not derive, design, test or draft reflection for the live personalised Written task with generated content. Add a group ledger with size, cells, stable variables, resulting term and uniquely useful coverage. Use it to justify wrap-around and overlap instead of relying on visual intuition. Compare two implementations under one stated gate library: total gate inputs, longest path and available test nodes.
Read both circuits back into expressions and verify all rows before discussing compactness. For debugging, freeze one failed assignment and trace input pins, inversions and internal nodes in topological order; the first mismatch localises the fault. After repair, rerun every stable row because one wiring change can alter previously passing cases.
Then run a separate transition observation and label any temporary output distinctly from the settled truth-table result. Save diagrams and test tables with matching node names and variable order so another reader can reproduce the reasoning without inferring wire crossings.
Maintain a clean copyright and assessment boundary: use the course-developed textbook to confirm gate meanings and simulator concepts, not to copy artwork, tables, circuit layouts or worked solutions. Keep every circuit and test record in this guide newly authored, and do not generate the live A1 design, evidence or reflection.
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