University of Queensland · FACULTY OF ELECTRICAL ENGINEERING

ELEC4410 Chap.9 Hardware Design and Verification

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Chapter 9 of 9 · ELEC4410

Hardware Design and Verification

Hardware verification follows the signal path in a fixed direction: reference and controller, PWM outputs, gate driver, switching bridge, filter, sensors and load. Checking the earliest stage first prevents several variables being changed together. If PWM is missing, investigate configuration, reference and enable conditions.

If PWM is correct but the switching node is wrong, move to driver reference, dead time, device orientation and supply.

A correct switching node with a wrong filtered output points toward the inductor, capacitor, load, sensor or measurement setup. This staged reasoning turns a failed waveform into evidence rather than a reason to replace parts randomly.

Preserve one observation, change one cause and record whether the failure boundary moved.

Measurement is part of the circuit. An oscilloscope reference can create an unintended current path, and a large probe loop can collect switching noise. Verify connections, polarity, grounds, supply limits and instrument references before energising. Power down before altering the circuit.

Safe sequencing is therefore both an operational requirement and a method for preserving causal evidence.

In this chapter

What this chapter covers

  • 01

    Controller

  • 02

    H-bridge and gate-driver path

  • 03

    Filter, sensing and load interfaces

  • 04

    Safe oscilloscope reference choices

  • 05

    Earliest-failed-stage diagnosis

Worked example · free

Diagnose a buck output that remains near zero

Q [4 marks]. The reference commands 25% duty but filtered output remains near zero. Give a safe, staged test sequence that isolates the earliest failed block. This practice split was written by AskSia and is not an official university mark allocation.
The blocks follow the laboratory energy path from command to load; measurements should move in the same order so the first incorrect stage is isolated.The blocks follow the laboratory energy path from command to load; measurements should move in the same order so the first incorrect stage is isolated.ControllerH-bridgeFilterMotor
The blocks follow the laboratory energy path from command to load; measurements should move in the same order so the first incorrect stage is isolated.
  • +1Verify controller pins produce the expected complementary PWM and dead time before probing the power stage.
  • +2Measure gate-driver output relative to the switch source, then observe the switching node with an appropriate safe reference.
  • +1If the switching node is correct, continue to inductor current, filtered output, load and sensor path, changing only one cause at a time.
Begin with the controller because it is the earliest command source. Confirm the expected PWM pair, duty and dead time. Next measure driver output relative to the relevant switch terminal rather than an arbitrary ground. With a safe measurement arrangement, inspect the switching node. A node that never rises points toward the driver, supply, connection, orientation or device conduction. A correct switching node with near-zero filtered output moves the boundary downstream to the inductor, capacitor, load, wiring or sensor. Record each observation, remove power before changing connections, and alter one suspected cause at a time so the diagnosis remains causal.
Sia tip — Probe from command toward load and stop at the first waveform that disagrees.
Glossary

Key terms

Hardware Design and
A core ELEC4410 topic used to organise controller, H-bridge, filter, sensing, safe energisation and staged diagnosis.
FAQ

Hardware Design and Verification FAQ

What must be checked before first power is applied?

Verify wiring, polarity, grounds, supply limits, device orientation and instrument references. Complete the required connection check before energising, then power down before making any circuit alteration.

How does an earliest-failed-stage diagnosis work?

Start at the reference and PWM command, then move through driver, switching node, filter and load. The first signal that departs from its predicted form bounds the fault without random component changes.

Why can an oscilloscope probe change the circuit?

Its reference connection may create an unintended current path, while a large loop collects high-frequency interference. Choose the reference deliberately, respect instrument limits and minimise the loop area.

Study strategy

Exam move

Draw the laboratory system as a left-to-right test chain: reference, controller, PWM, driver, bridge, switching node, filter, sensor and load. For each boundary, sketch the waveform expected when everything upstream is correct. Practise diagnosing three cases without touching the circuit: missing PWM, correct gate command with a wrong switching node, and correct switching node with excessive output ripple.

Write the safe probe reference beside each measurement and mark when power must be removed. In a lab plan, one action should test one hypothesis; avoid changing controller settings, wiring and filter parts together. Finish by matching every analytical prediction from earlier chapters to a measurable node, current or temperature.

Verification is strongest when the calculation and the instrument tell the same state-by-state story. Build a fault log with columns for predicted waveform, observed waveform, earliest disagreement, single intervention and result. Add supply limits, probe scale and reference to every trace. Rehearse the power-off sequence before changing any connection, including stored-energy discharge.

For sensor faults, compare the feedback reading with an independent safe measurement before adjusting controller parameters. This preserves the original evidence and prevents a calibration error from being misdiagnosed as an unstable bridge End each practice diagnosis with a safe next measurement rather than a replacement guess.

Check that the proposed probe reference cannot short a floating node, and write the evidence that would move the fault boundary downstream before any filter or load component is changed Finish by recording the first incorrect stage and the evidence required before moving farther toward the load Preserve the original trace before changing hardware.

Working through Hardware Design and Verification in ELEC4410? Sia is AskSia’s AI Electrical Engineering tutor — ask any ELEC4410 Hardware Design and Verification question and get a clear, step-by-step explanation grounded in how ELEC4410 is taught and assessed. Read this chapter free, then take your hardest questions to Sia.

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