FIT2100 Chap.1 Computer Architecture and Interrupts
Computer Architecture and Interrupts
This chapter connects the processor, registers, cache, main memory, buses and input or output controllers to the operating system that manages them. The essential story is control transfer. Normal work follows the fetch, decode and execute cycle.
A device or timer can interrupt that stream, causing the processor to preserve context and enter a trusted service routine before execution resumes.
Revision should distinguish where data lives, what each register records and why interrupts improve utilisation. Cache is a fast copy of selected memory content, not a second permanent store. Main memory must contain active instructions and data.
Controllers expose registers through which drivers command a device and read status. An interrupt is an event-driven detour, not proof that the running process has failed.
What this chapter covers
- 01
CPU registers and the instruction cycle
- 02
Program counter and instruction register
- 03
Main memory and volatility
- 04
Cache and locality
- 05
System buses and controllers
- 06
Interrupt sources and vectors
- 07
Context preservation and restoration
- 08
Operating system as resource manager
Worked example · free
Trace a disk-completion interrupt
- +2The processor completes the current instruction, saves essential status and uses the interrupt vector to enter the disk handler.
- +2Entry code preserves remaining registers. The handler acknowledges completion and updates the waiting request, which can make a blocked process ready.
- +2The scheduler chooses an eligible process. Its saved context is restored, and execution returns without treating the interrupt as process termination.
Key terms
- Program Counter
- The processor register that identifies the next instruction position in the executing stream.
- Instruction Register
- The register holding the instruction currently being decoded or executed.
- Cache Memory
- Small, fast storage containing copies of selected main-memory content to exploit locality.
- Main Memory
- Volatile storage that holds programs and data while they are active and directly addressable by the processor.
- Interrupt Vector
- The mapping that directs a particular interrupt source to its service routine.
- Device Controller
- Hardware that connects a device to the system bus and exposes command, status and data registers.
Computer Architecture and Interrupts FAQ
Why are interrupts better than waiting in a loop?
A waiting loop repeatedly consumes processor cycles while checking whether a slow device has finished. Interrupt-driven completion allows useful work to run until the controller signals the event. There is still entry and handler overhead, but the CPU is not occupied by continuous status checks.
Does an interrupt always switch to a different process?
No. An interrupt transfers control to a handler, but the scheduler may restore the same process if it remains the best eligible choice. The handler can also make another process ready, in which case policy determines what runs next.
What is saved when an interrupt occurs?
Hardware typically preserves essential processor status such as the program counter, while entry code saves additional working registers into the current process context. The exact division is architecture dependent, but enough state must remain to resume correctly.
How are cache and main memory different?
Cache is smaller and faster and normally stores copies of recently useful memory regions. Main memory holds the active program and data set. A cache miss asks the memory hierarchy for the required content; it does not mean the address is invalid.
Assessment move
Draw the hardware path from CPU to cache, memory, controller and device, then annotate where an interrupt changes control. Practise explaining one event in strict order without saying only that the operating system handles it. Test yourself on register roles, volatility, locality and the difference between polling and interrupts. For a demonstration, point to the event source, the vector, the saved context and the return path.
Clear sequencing aligns with the applied rubric better than a long list of component names. Build a two-column trace for every scenario: one column records the instruction stream and saved processor state, while the other records the controller command, status change and interrupt. At each row, ask whether data moved, control moved, or both.
Redraw the memory hierarchy from fastest and smallest to slowest and largest, then label volatility and whether each level normally contains an original object or a copy. Use a fresh device example, such as keyboard input or a timer tick, to verify that the interrupt reasoning is not tied only to disks.
When reviewing a mistaken answer, identify the first boundary it crosses incorrectly: cache versus main memory, controller versus device, user code versus handler, or ready versus running. Finish by giving a sixty-second oral explanation with no diagram, then reproduce the diagram from that explanation. This alternation tests whether the arrows carry meaning rather than decoration.
In applied work, collect one observation that supports each step, such as a return value, state print or ordered log message, and explain why that observation is consistent with the model without claiming that print timing alone proves the hardware sequence.
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