University of Sydney · FACULTY OF ELECTRICAL ENGINEERING

ELEC5206 Chap.8 Dynamic Modelling and Voltage Control of the PVSC

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Chapter 8 of 14 · ELEC5206

Dynamic Modelling and Voltage Control of the PVSC

This chapter combines the PVSC control lecture with the lecture on relative stability. It argues for regulating PV voltage rather than PV current, places MPPT outside the feedback loop as the source of the voltage reference, and derives the boost PVSC’s averaged and small-signal models.

Linearising the PV curve with its negative dynamic resistance gives a second-order transfer function from duty ratio to PV voltage, whose damping falls as the operating point moves into the current-source region. A controller is then designed by affine parameterisation: choose the closed-loop response, solve for the controller, and map it to PID gains.

Finally the loop is judged by phase margin, gain margin and sensitivity peak, read from Bode and Nyquist plots. Expect derivations, parameter calculations and a robustness judgement.

In this chapter

What this chapter covers

  • 01

    Why PV voltage, not PV current, is regulated

  • 02

    Two loops: the PVSC voltage loop and the DC-link loop

  • 03

    Averaged and small-signal models of the boost PVSC

  • 04

    Dynamic resistance and the second-order duty-to-voltage plant

  • 05

    Natural frequency, damping and the current-source region

  • 06

    Affine parameterisation and the resulting PID gains

  • 07

    Absolute, internal and relative stability

  • 08

    Phase margin, gain margin and sensitivity peak

Worked example · free

PID time constant and integral gain from an affine design

Q [4 marks]. A boost PVSC plant has ωn = 25.8 krad/s and K0 = −3.99 × 1010. The target loop has ζcl = 0.7 and ωcl = 4ωn. Find α1, α2, τd and Ki. The 4-mark allocation is our own practice weighting, not the university's marking scheme.
  • 1ωcl = 4 × 25,797 = 103,187 rad/s.
  • 1α1 = 2ζcl/ωcl = 1.4/103,187 = 1.357 × 10−5 s and α2 = 1/ωcl² = 9.39 × 10−11 s².
  • 1τd = α2/α1 = 6.92 × 10−6 s.
  • 1Ki = ωn²/(K0α1) = 6.655 × 108/(−3.99 × 1010 × 1.357 × 10−5) = −1228.
α1 = 1.36 × 10−5 s, α2 = 9.39 × 10−11 s², τd = 6.92 µs and Ki = −1228; the negative sign follows from the negative plant gain.
Sia tip — Keep K0 negative all the way through; a positive integral gain on this plant would turn negative feedback into positive feedback.
Glossary

Key terms

Dynamic resistance
The local slope RPV = ΔV/ΔI of the PV curve, negative at every operating point.
Damping ratio
The parameter ζ of a second-order system that measures how quickly oscillations decay.
Affine parameterisation
A design method that chooses the desired closed loop FQ and solves for the controller C = Q/(1 − QG0).
Phase margin
180° plus the loop phase at the frequency where the loop gain magnitude equals one.
Gain margin
The factor by which loop gain could rise before instability, 1/|CG0| at the phase crossover.
Sensitivity peak
The maximum of 1/|1 + CG0|, equal to one over the Nyquist curve's closest distance to minus one.
FAQ

Dynamic Modelling and Voltage Control of the PVSC FAQ

Why is the PVSC plant hard to control near the current-source region?

Damping is inversely proportional to the magnitude of the dynamic resistance. On the flat, current-source part of the I-V curve that magnitude is large, so damping falls and the loop oscillates; the lecture flags this as an oscillation alert and advises avoiding that region.

Why are the controller gains negative in the case study?

The plant gain K0 equals minus the DC-link voltage divided by the product of inductance and PV capacitance, so it is negative: raising the boost duty ratio lowers the PV voltage. The affine design divides by K0, so every PID gain inherits the negative sign, which keeps the overall feedback negative.

Is a stable loop automatically good enough?

No. Affine design guarantees input-output and internal stability, but robustness, the distance from instability, is judged separately by phase margin, gain margin and sensitivity peak. The lecture rejects a stable controller with a 32.5° phase margin and a sensitivity peak of 2.44 as not robust enough.

Why does MPPT sit outside the voltage feedback loop?

MPPT decides where the PV voltage should be and changes that reference slowly, while the voltage loop keeps the PV voltage at the reference against fast disturbances. Separating the two lets each be designed for its own time scale, and the lecture shows that tracking becomes much faster once a dedicated voltage loop is present.

Study strategy

Exam move

Derive the small-signal model once from the switching equations, writing every step, then practise only the final three formulas for ωn, ζ and K0 with your own component values. Memorise the four affine design steps as a sentence each.

For stability, practise reading margins from a Bode plot and computing one margin by hand from magnitudes and angles, and always finish with a verdict on robustness. Explain aloud why a lightly damped plant needs a well-designed loop.

Working through Dynamic Modelling and Voltage Control of the PVSC in ELEC5206? Sia is AskSia’s AI Electrical Engineering tutor — ask any ELEC5206 Dynamic Modelling and Voltage Control of the PVSC question and get a clear, step-by-step explanation grounded in how ELEC5206 is taught and assessed. Read this chapter free, then take your hardest questions to Sia.

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