ELECTENG 101 Chap.4 Signal Conditioning and Op-Amp Circuits
Signal Conditioning and Op-Amp Circuits
Signal conditioning protects and reshapes sensor voltages before conversion or control. Source resistance and receiver input resistance create loading. Buffers reduce that interaction. Closed-loop op-amp circuits then provide gain, inversion, summing and offset, provided negative feedback is present and the requested output remains inside physical input and output limits.
The useful design target is often an affine map that stretches a sensor span and shifts its baseline into an ADC or controller range. Ideal analysis uses negligible input current and nearly equal input voltages only when negative feedback maintains linear operation. A symbolic gain can be algebraically correct yet physically impossible if the output requires a rail voltage the amplifier cannot reach.
A complete design therefore follows the entire chain from loaded source through transfer equation to endpoint and saturation checks.
What this chapter covers
- 01
Thevenin source loading
- 02
Input and output resistance
- 03
Voltage follower buffering
- 04
Ideal op-amp constraints
- 05
Inverting and non-inverting gain
- 06
Summing and level shifting
- 07
Output saturation
Worked example · free
Fit gain and offset
- +2Choose Rin = 10 kΩ to obtain gain −2.
- +3Choose Rref = 20 kΩ so the −1 V reference contributes +1 V.
- +2Check endpoint outputs against the available rails.
Key terms
- Loading effect
- A change in source output caused by current drawn by the connected receiving circuit.
- Voltage follower
- A unity-gain feedback stage used for high input resistance and low output resistance.
- Virtual node
- A node held near another input voltage by feedback without a direct conductive connection.
- Saturation
- The condition where a requested output exceeds the achievable output swing.
Signal Conditioning and Op-Amp Circuits FAQ
When may I use equal op-amp input voltages?
Use the ideal equality only when negative feedback is present and the output is not saturated. It is not a rule for an open-loop comparator or a rail-limited result. First identify a feedback path from output to the inverting input and verify that a small output change drives the input difference back toward zero rather than reinforcing it.
Why buffer a divider?
A buffer draws negligible input current in the ideal model, preserving the divider voltage while providing a low-resistance output for the next stage. Its voltage gain is approximately one, so the benefit is isolation rather than amplitude increase. Place it at the interface whose source resistance is high relative to the receiving input resistance.
How do I diagnose a wrong amplifier output?
Check the actual loaded input, confirm the feedback sign and compare the requested output with the rails. These identify loading, positive feedback and saturation as different faults. Then test two input endpoints in the symbolic transfer function; a reversed slope, wrong intercept or unequal endpoint error reveals which resistor ratio or reference contribution was set incorrectly.
What is an affine voltage map?
It is a relation of the form output equals gain times input plus an offset. Two input-output endpoint pairs determine the required slope and intercept. Op-amp gain networks implement the slope, while a reference contribution creates the offset. Checking both endpoints is stronger than verifying only one convenient input value.
Why is a virtual ground not a real ground?
Negative feedback may hold an inverting input near a grounded non-inverting input, but no physical ground conductor is connected there. The node cannot freely source or sink arbitrary current; currents flow through the attached resistors and the op-amp input ideally draws none. Treating it as wired ground can erase the summing equation.
How does saturation change an amplifier calculation?
When the ideal transfer demands an output beyond the available swing, the real output clips near a supply limit and the equal-input approximation no longer supports the calculated value. Report the requested ideal output, identify the violated rail, and state the clipped behaviour rather than continuing later stages with an impossible voltage.
Exam move
Solve each design as a sequence of transfer blocks. Determine the sensor range, loaded interface output, required affine map and destination range. Write KCL at the op-amp summing node with signed currents and test two endpoint values. Always check rails and loading after the symbolic result. Rework one example by reversing the desired direction so that inversion and offset choices become deliberate rather than memorised.
Build a block ledger with source resistance, input resistance, transfer equation and allowed output range for each stage. Start with a buffer-only example to distinguish isolation from gain. Then derive inverting, non-inverting and summing relations from KCL instead of recalling formulas without their conditions.
Design one endpoint map with positive slope and another with negative slope, choosing a reference that produces the needed intercept. For each, test the minimum, midpoint and maximum inputs against both supply rails. Finally introduce a finite receiver load and decide whether the earlier output-resistance assumption remains acceptable.
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