ELEC4602 Chap.7 Data Converters and Sampling Architectures
Data Converters and Sampling Architectures
Week 7 moves from sampling into the structures that translate between analogue values and digital codes. The syllabus names current-steering and charge-scaling DACs, plus flash and successive-approximation ADCs.
Revision should centre on architecture rather than unsupported numerical claims: what elements create the reference levels, how a code selects or combines them, where a comparator acts, how many decisions occur and which physical mismatches become visible. Converter metrics then provide the language for describing whether the transfer from value to code, or code to value, is acceptable.
What this chapter covers
- 01
Sampling before conversion
- 02
Converter transfer and error metrics
- 03
Current-steering DAC structure
- 04
Charge-scaling DAC structure
- 05
Flash ADC parallel decisions
- 06
Successive-approximation ADC search
Worked example · free
Choose between flash and successive approximation
- +1Map the very fast requirement to the flash structure because it compares against many reference levels in parallel.
- +1State the flash cost as extensive comparator and reference hardware, with matching and input loading requiring attention.
- +1Map the compact repeated-decision requirement to successive approximation, which reuses comparison around an internal search.
- +1Verify conversion timing and transfer behaviour for each architecture, rather than declaring one universally superior.
Key terms
- Data converter
- A data converter maps between an analogue quantity and a digital code according to a defined transfer relationship.
- Current-steering DAC
- A current-steering DAC forms an output by directing selected current elements according to the input code.
- Charge-scaling DAC
- A charge-scaling DAC combines switched capacitor contributions to create a code-dependent analogue level.
- Flash ADC
- A flash ADC compares an input with many reference levels in parallel before encoding the decision pattern.
- Successive approximation ADC
- A successive-approximation ADC resolves a code through a sequence of internal trial values and comparator decisions.
- Transfer characteristic
- A transfer characteristic relates analogue input or output level to the corresponding digital code.
Data Converters and Sampling Architectures FAQ
Why is a flash ADC fast?
It makes many threshold comparisons in parallel, so the architecture does not need a long serial search through candidate codes. The trade-off is the amount of comparator and reference hardware, which increases loading, matching burden and implementation cost. Speed must therefore be assessed with those physical costs.
How does successive approximation make a decision?
It proposes an internal trial value, compares that value with the input and keeps or rejects the corresponding decision before moving to the next step. The same decision path is reused across the conversion. Timing and settling at each step are therefore central to correct operation.
What should I include in a converter comparison?
Name the signal path, decision structure, conversion timing, hardware burden and the physical error most likely to matter. For a DAC, explain how code elements combine into an analogue output. For an ADC, explain how references and comparisons divide the input range into codes.
Exam move
Draw each converter as a flow of information and physical quantity. For a current-steering DAC, follow the code into element selection and the selected currents into the output. For a charge-scaling DAC, follow switch states into stored charge and the resulting level. For a flash ADC, follow the input across the comparator bank and then into encoding.
For successive approximation, follow one trial, comparison and retained decision before repeating the logic. Under every diagram, write four headings: speed, hardware, dominant physical sensitivity and verification. Use those headings to answer architecture-choice questions rather than relying on a memorised ranking.
Practise reading a qualitative transfer characteristic and describing what an error would look like without inventing specifications absent from the source. Finally, connect sampling to conversion: the converter can only act on the value presented to it, so acquisition, hold disturbance and settling belong in the same verification story.
Create a second table for interfaces: source or code input, reference path, decision or combining element, output load and observation instant. Use it to explain why an internally plausible converter can fail when the sampled input or reference is unsettled. For a search architecture, narrate trial, settle, compare and retain in order; for a parallel architecture, trace loading and encoding.
For each DAC, identify which physical elements change at a difficult code boundary. Finish with one isolated-core test and one full signal-chain test so architecture behaviour and interface behaviour are not confused.
Working through Data Converters and Sampling Architectures in ELEC4602? Sia is AskSia’s AI Electrical Engineering tutor — ask any ELEC4602 Data Converters and Sampling Architectures question and get a clear, step-by-step explanation grounded in how ELEC4602 is taught and assessed. Read this chapter free, then take your hardest questions to Sia.
