ELEC4602 Microelectronic Design & Tech
The Complete Exam Bible · T3 2026ELEC4602 Overview
- UNSW Sydney
- Term 3 2026
- Level 4 honours
- Final examination is largest component
ELEC4602 Microelectronic Design & Tech is a Level 4 electrical engineering course at UNSW Sydney. The Term 3 2026 Moodle sequence begins with CMOS processing, physical components, layout layers and design rules.
- Largest assessment The final examination contributes 60% of the published course mark.
- Quiz route Quiz 1 covers Weeks 1 to 3, while Quiz 2 covers Weeks 4 to 7.
- Design evidence Strong reports connect architecture, implementation, measured performance and verification.
- Revision spine Trace every circuit from physical structure through model, test and system consequence.
What you get in the full ELEC4602 Exam Bible
- 10 chapters, 55 pages — every examinable topic, week by week
- 29 original practice questions, most with model answers in the Final examination format
- 10 worked examples, solved the way ELEC4602 marks
- 10 computed figures, redrawn from the course’s own numbers
- Exam-morning plan for the Final examination (60%) — what to revise last, where marks are lost
Free on this page: assessment table, chapter map, one worked example, key terms, FAQ. The rest is in the full exam bible.
How ELEC4602 is assessed
| Component | Weight | Format |
|---|---|---|
| Laboratory work | 15% | Group laboratory exercises and reports across the teaching term |
| Quizzes | 10% | Two in-class quizzes: Quiz 1 covers Weeks 1 to 3 and Quiz 2 covers Weeks 4 to 7 |
| Design task | 15% | Group design task undertaken during the flexibility week, assessed through design and verification evidence |
| Final examination | 60% | Individual final examination; use the current Moodle exam notice for duration, sections and permitted materials |
What other students are asking about ELEC4602
- Where can I find lecture notes or study guides for ELEC4602 at UNSW?
- The ELEC4602 study guide in AskSia Library covers Microelectronic Design & Tech in 10 chapters, with the assessment table, a chapter-by-chapter topic map, key terms and a worked example, free to read on this page.
- Is there a final exam in ELEC4602, and how much is it worth?
- Yes. In the offering this AskSia Library guide is built from, Final examination carries 60% of the ELEC4602 mark; the full split is Laboratory work 15%, Quizzes 10%, Design task 15%, Final examination 60%.
- What does ELEC4602 cover on ic design flow and mos models?
- In AskSia Library's ELEC4602 guide, the IC Design Flow and MOS Models chapter explains simulation, extraction, LVS and model choice from Week 2.
- What does ELEC4602 cover on mos devices, noise and current mirrors?
- In AskSia Library's ELEC4602 guide, the MOS Devices, Noise and Current Mirrors chapter explains operating regions, noise sources and bias structures from Week 3.
- What does ELEC4602 cover on amplifier stages and operational amplifiers?
- In AskSia Library's ELEC4602 guide, the Amplifier Stages and Operational Amplifiers chapter explains single-stage topologies, differential pairs and op-amps from Week 4.
What ELEC4602 covers
ELEC4602 moves from fabrication and layout into MOS modelling, noise and analogue building blocks, then through sampling and data conversion to CMOS logic, timing and memory. The sequence follows the ten substantive teaching weeks in the Term 3 2026 Moodle syllabus.
Fabrication, Layout and Design Rules
Process steps, IC layers and layout checks from Week 1The opening ELEC4602 topic connects wafer processing to the geometry a designer draws.
- Wafer processing and layer formation
- Lithography as selective pattern transfer
- Implantation, etching and deposition
- Active, polysilicon, contact and metal layers
- Design-rule checks before fabrication
- From layout geometry to electrical intent
IC Design Flow and MOS Models
Simulation, extraction, LVS and model choice from Week 2Week 2 puts analogue, mixed-mode and digital work into one verified design flow. Requirements lead to circuit design or HDL design, followed by simulation, layout or place-and-route, extraction, post-layout simulation, top-level integration and tapeout.
- Requirements before implementation
- Analogue, mixed-mode and digital paths
- Pre-layout versus post-layout simulation
- Extraction and layout-versus-schematic checking
- Top-level integration and tapeout
- Choosing a MOS model for the question
MOS Devices, Noise and Current Mirrors
Operating regions, noise sources and bias structures from Week 3Week 3 joins three ideas that should be revised together. MOS bias establishes an operating region and therefore the device behaviour available to a circuit. Small-signal parameters describe how that biased device responds to a perturbation.
- MOS bias and operating regions
- Large-signal and small-signal viewpoints
- Parasitic capacitance and switching behaviour
- White and low-frequency noise
- Device noise referred through a circuit
- Current-mirror bias and output branches
Amplifier Stages and Operational Amplifiers
Single-stage topologies, differential pairs and op-amps from Week 4Week 4 develops single-stage amplifiers, cascodes, differential pairs and the two-stage operational amplifier. The useful exam skill is not naming topologies in isolation; it is choosing a signal path and explaining the trade-off that follows.
- Common-source signal inversion and gain
- Common-drain buffering
- Common-gate and cascode signal paths
- Differential-pair steering
- Two-stage operational-amplifier structure
- Gain-bandwidth and slew-rate verification
Compensation, Comparators and Sampling
Stability, decision circuits and charge injection from Week 5Week 5 links amplifier stability to decision circuits and sampled signals. Compensation deliberately reshapes dynamic behaviour so a feedback amplifier can settle rather than oscillate.
- Operational-amplifier compensation
- Sizing and output-stage choices
- Continuous comparator paths
- Latched comparator regeneration
- Sampling and held-state accuracy
- Charge injection and offset control
Design Task, Verification and Reporting
Design evidence, testing and documentation for the Week 6 taskThe Week 6 flexibility period is assigned to the design task, and the official rubric reveals how the work is judged. Understanding means explaining the chosen architecture, operation, implementation and limitations.
- Requirements translated into tests
- Architecture choice and limitations
- Implementation using standard conventions
- Performance compared with specifications
- Deterministic and statistical verification
- Legible technical documentation
Data Converters and Sampling Architectures
Converter metrics, DAC structures and ADC choices from Week 7Week 7 moves from sampling into the structures that translate between analogue values and digital codes. The syllabus names current-steering and charge-scaling DACs, plus flash and successive-approximation ADCs.
- Sampling before conversion
- Converter transfer and error metrics
- Current-steering DAC structure
- Charge-scaling DAC structure
- Flash ADC parallel decisions
- Successive-approximation ADC search
CMOS Inverters, Delay and Power
Transfer behaviour, fan-out, switching and energy from Week 8Week 8 uses the CMOS inverter to connect transistor behaviour with digital-system measures. The voltage transfer characteristic shows where the output changes state and how the input and output levels create noise margins.
- CMOS inverter pull-up and pull-down
- Voltage transfer characteristic
- Logic levels and noise margins
- Switching path and capacitive load
- Inverter sizing and fan-out
- Static CMOS gate construction
Static and Sequential Logic
Gate synthesis, latches, flip-flops and timing from Week 9Week 9 extends static CMOS into complex gates, physical layout and sequential storage.
- Complex static CMOS synthesis
- Gate layout and sizing
- Transmission gates and multiplexers
- Latch and flip-flop state
- Setup and hold relationships
- Static versus dynamic storage
Semiconductor Memory Design
ROM, SRAM, DRAM and sense paths from Week 10Week 10 closes the course with dynamic registers and semiconductor memories: ROM, SRAM, DRAM, array organisation, performance, sense amplifiers and floating-gate memory. Each memory family stores information through a different physical mechanism.
- Memory array organisation
- ROM programmed state
- SRAM bistable storage
- DRAM charge storage and refresh
- Read and write paths
- Sense amplifiers and floating-gate memory
It then connects those physical choices to the analogue, mixed-mode and digital design flows used to turn requirements into simulated, laid-out and verified integrated circuits. The middle of the course develops MOS operating behaviour, device noise, current mirrors, single-stage amplifiers, differential pairs, operational amplifiers, compensation, comparators and sampled circuits.
The later weeks shift to data-converter architectures, CMOS inverter behaviour, combinational and sequential logic, and semiconductor memories. This guide follows that progression because each later decision depends on the earlier physical and modelling assumptions. The published assessment structure places 15% on laboratory work, 10% on quizzes, 15% on a design task and 60% on the final examination.
Quiz 1 tests Weeks 1 to 3 and Quiz 2 tests Weeks 4 to 7. Use the current Moodle exam notice for the course-specific final duration, section layout, aids rule and any operational conditions. The guide prepares the central reasoning: classify a device or architecture, explain a signal or verification path, compare alternatives against requirements, and state what evidence would demonstrate that the design works.
The official rubric makes the marking logic unusually clear. High-quality work explains the selected architecture and its limits, implements it using standard conventions, measures performance against the requirements, verifies the relevant behaviours and presents legible figures and concise documentation. Those same habits organise every chapter here.
Worked example · free
Recover the IC design flow after a failed post-layout check
- +1Name the boundary: the schematic result was based on the pre-layout model, while the failed check includes extracted physical effects.
- +1Return to the affected device sizing, topology, routing or loading assumption instead of advancing to tapeout.
- +1Repeat the relevant post-layout simulation with the extracted view and compare the same requirement against the new result.
- +1Document the cause, the change and the before-versus-after evidence so the verification trail is reproducible.
Key terms
- Lithography
- The pattern-transfer step that defines where later processing acts on a wafer.
- Design rule
- A geometric constraint that keeps a layout compatible with the manufacturing process.
- Extraction
- The conversion of layout geometry into an electrical view used for post-layout checks.
- Layout versus schematic
- A connectivity check that compares the extracted layout network with the intended schematic.
- Operating region
- The bias-defined mode that determines which MOS device model is appropriate.
- Current mirror
- A bias circuit that reproduces a reference current in one or more output branches.
- Differential pair
- An input stage that responds primarily to the voltage difference between two inputs.
- Compensation
- A deliberate change to an amplifier's dynamic response that improves closed-loop stability.
- Charge injection
- Unwanted charge transferred from a switching device into a sampled node.
- Successive approximation ADC
- A converter that resolves a code through a sequence of comparator decisions.
- Noise margin
- The allowable voltage disturbance between guaranteed logic output and input levels.
- Sense amplifier
- A circuit that detects and enlarges a small memory-cell read signal.
ELEC4602 FAQ
How is the course assessed?
The published Term 3 2026 structure is laboratory work 15%, quizzes 10%, design task 15% and final examination 60%. Those numeric rows sum to 100%. Use the current Moodle assessment page for any operational condition attached to the assessments.
What does the final examination cover?
The official table labels a final examination worth 60%, while the weekly syllabus spans fabrication, MOS models, analogue circuits, sampling, converters, CMOS logic and memory. Prepare across the taught sequence and use the current Moodle exam notice for the course-specific duration, section split, question types and aids rule.
What material is tested in the quizzes?
Quiz 1 is an in-class quiz on material from Weeks 1 to 3. Quiz 2 is an in-class quiz on Weeks 4 to 7. Together the quizzes contribute 10% of the course mark. Treat that as the combined published quiz weight and use the current assessment page for any operational breakdown.
What earns marks in the design task?
The official rubric rewards understanding of the design, correct implementation, technical performance, verification and documentation. Strong work explains why an architecture fits the requirement, tests the important behaviours, relates results back to specifications and makes figures readable. It is not enough to present a schematic or simulation without the reasoning chain that connects them.
Are the practice questions original?
Yes. The practice questions in this guide are newly authored from the published topic sequence and rubric priorities. They do not reproduce or lightly reword proprietary assessment questions, and they do not imply a particular final-exam section, duration, question type or marks allocation.
How should I revise efficiently?
Start with the physical-to-electrical chain: process step, layout, extracted model and verified behaviour. Then rehearse one comparison for each major family: MOS region choice, amplifier topology, comparator or sampler error, converter architecture, logic timing and memory cell. Finish by writing short evidence-led answers that name the requirement, mechanism, test and conclusion.
Questions students ask in each ELEC4602 chapter
- Why do layout rules matter if the schematic is correct?
- A schematic records electrical intent, while layout determines the physical shapes that manufacturing must reproduce. A logically correct netlist can still fail if a feature is too narrow, two shapes are too close or a contact lacks enclosure. Design-rule checking protects the translation from electrical intent to process-compatible geometry. Chapter 01 · Fabrication, Layout and Design Rules
- Why is the design flow drawn with feedback loops?
- Integrated-circuit design is not a one-way sequence. A requirement can fail after schematic simulation, layout extraction or top-level integration, and each failure points back to a different decision. The loops make verification an active design step: evidence determines whether the work advances or returns for correction. Chapter 02 · IC Design Flow and MOS Models
- Why must I check the operating point before small-signal analysis?
- The small-signal model is built around a particular bias state. If the device is actually in another region, the assumed incremental parameters and gain path no longer describe the circuit. Reporting a small-signal result without first checking the operating point can make a mathematically neat answer physically irrelevant. Chapter 03 · MOS Devices, Noise and Current Mirrors
- How do I compare amplifier topologies in an exam answer?
- Use the same axes for every option: input loading, voltage gain, inversion, output resistance, headroom and bandwidth. Then connect the winning axis to the stated requirement. A list of remembered properties is weaker than a choice that explains why one topology fits the source and load. Chapter 04 · Amplifier Stages and Operational Amplifiers
- Why does compensation trade speed for stability?
- Compensation changes where the amplifier's dynamic response loses gain and accumulates phase shift. Making the closed-loop system more tolerant of feedback can reduce the speed available for a given transition. A good answer states the intended feedback condition and verifies both settling behaviour and the performance cost. Chapter 05 · Compensation, Comparators and Sampling
- What does the design rubric reward?
- It rewards five connected outcomes: understanding of the design, correct implementation, technical performance, verification and documentation. The strongest work explains the architecture and its limits, implements it clearly, measures the important behaviours, tests the relevant conditions and communicates the evidence in a concise, legible report. Chapter 06 · Design Task, Verification and Reporting
- Why is a flash ADC fast?
- It makes many threshold comparisons in parallel, so the architecture does not need a long serial search through candidate codes. The trade-off is the amount of comparator and reference hardware, which increases loading, matching burden and implementation cost. Speed must therefore be assessed with those physical costs. Chapter 07 · Data Converters and Sampling Architectures
- How does the inverter VTC connect to noise margin?
- The transfer curve identifies the regions treated as valid low and high input or output levels and the transition between them. Noise margins compare the guaranteed output levels with the receiving input boundaries. A wider separation means a larger disturbance can occur without changing the interpreted logic state. Chapter 08 · CMOS Inverters, Delay and Power
- Why can sequential logic fail when the truth table is correct?
- A truth table describes stable logical relationships, not whether a storage element sees valid data at the required time. Clocked circuits add timing constraints, internal state and physical delays. A correct function can therefore fail during capture if data or clock paths violate the storage element's timing boundary. Chapter 09 · Static and Sequential Logic
- What is the central difference among ROM, SRAM and DRAM?
- The storage mechanism differs. ROM represents a programmed state, SRAM maintains a bistable circuit state while powered, and DRAM stores charge that leaks and therefore needs refresh. Those mechanisms determine density, read and write behaviour, peripheral circuitry and the tests needed to demonstrate reliable operation. Chapter 10 · Semiconductor Memory Design
How to study for the exam
Use four passes. First, build a physical map from fabrication step to layout layer and design rule. Second, connect each MOS operating idea to the circuit blocks that depend on it: mirrors, amplifier stages, differential pairs and comparators. Third, practise architecture decisions across sampling, data conversion, CMOS logic and memory, always naming the requirement that drives the choice.
Fourth, rehearse verification writing. For every design, state the intended behaviour, choose a test that exposes it, describe the result and decide whether the specification is met. This matches the official rubric's emphasis on understanding, implementation, technical performance, verification and documentation.
Revise the quiz ranges separately: Weeks 1 to 3 for Quiz 1 and Weeks 4 to 7 for Quiz 2. Before the final, reconnect the sequence so that a physical choice can be followed through its model, circuit effect, system consequence and verification method. Do not assume a duration, section structure or permitted-aids rule from another UNSW course; use the current Moodle exam notice for those operational details.
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