ELEC4602 Chap.2 IC Design Flow and MOS Models
IC Design Flow and MOS Models
Week 2 puts analogue, mixed-mode and digital work into one verified design flow. Requirements lead to circuit design or HDL design, followed by simulation, layout or place-and-route, extraction, post-layout simulation, top-level integration and tapeout. The feedback arrows matter more than the labels: a failed requirement sends the design back to the decision that created it.
The same week introduces MOS models, which means every analysis must use a representation appropriate to the question instead of treating one model as universally valid.
What this chapter covers
- 01
Requirements before implementation
- 02
Analogue, mixed-mode and digital paths
- 03
Pre-layout versus post-layout simulation
- 04
Extraction and layout-versus-schematic checking
- 05
Top-level integration and tapeout
- 06
Choosing a MOS model for the question
Worked example · free
Route a post-layout timing failure
- +1Locate the first changed representation: extraction added physical loading and interconnect effects absent from the earlier view.
- +1Inspect the critical path, loading, cell choice and routing rather than repeating an unchanged RTL simulation.
- +1Revise the responsible implementation decision, regenerate the physical view and repeat the post-layout timing check.
- +1Advance only when the extracted result satisfies the requirement and the implementation still passes connectivity and integration checks.
Key terms
- Specification
- A specification turns the intended circuit behaviour into a requirement that can be designed and verified.
- SPICE simulation
- SPICE simulation predicts circuit behaviour from an electrical network and the selected device models.
- Place and route
- Place and route maps a digital netlist into positioned cells and physical interconnections.
- Extraction
- Extraction derives a post-layout electrical representation that includes the implemented connectivity and physical effects.
- Post-layout simulation
- Post-layout simulation retests behaviour using the extracted physical representation rather than the ideal schematic view.
- Tapeout
- Tapeout is the release of the completed and verified layout for fabrication.
IC Design Flow and MOS Models FAQ
Why is the design flow drawn with feedback loops?
Integrated-circuit design is not a one-way sequence. A requirement can fail after schematic simulation, layout extraction or top-level integration, and each failure points back to a different decision. The loops make verification an active design step: evidence determines whether the work advances or returns for correction.
What is the difference between extraction and LVS?
Extraction produces an electrical representation from the physical layout, including implemented connectivity and relevant physical effects. Layout-versus-schematic checking asks whether that extracted connectivity matches the intended schematic. They are related but answer different questions: what was built, and whether it is the intended network.
How do I choose a MOS model for an answer?
Start from the quantity being asked about. A region or current question needs a large-signal operating view; a small variation around a bias point needs a small-signal view; a logic transition may use a simplified switching model. State the model boundary so the reader knows which effects are retained or ignored.
Exam move
Redraw the course design flow from memory, but add a question beside every arrow. At requirements, ask what success means. At simulation, ask which model and corner are being used. At layout, ask whether the geometry obeys process rules. At extraction, ask what new physical effects enter. At post-layout verification, ask whether the same specification still passes.
At integration, ask whether interfaces and timing remain valid. This converts a memorised flowchart into a diagnostic method. Then practise short failure scenarios: a connectivity mismatch, a timing failure, a degraded analogue response or an integration problem.
For each, identify the first representation that differs from a passing result, trace backward to the responsible design choice and name the evidence required before advancing. Review MOS models in parallel by writing one sentence on what each model can answer and one effect it omits.
The final habit is to state the verification boundary explicitly, because 'simulation passed' is meaningless unless the model, view and requirement are named. Make a representation ledger beside the flow. For behavioural, transistor, layout and extracted views, record what becomes visible and what can still be hidden. Use the ledger to compare two otherwise identical tests and locate the earliest changed assumption.
Practise a mixed-mode interface failure by naming the expected level, load and timing on each side. Before advancing, require one exit artifact: a passing requirement check, connectivity proof or integrated trace. This turns tapeout into an evidence-backed release decision rather than the end of a memorised sequence.
Working through IC Design Flow and MOS Models in ELEC4602? Sia is AskSia’s AI Electrical Engineering tutor — ask any ELEC4602 IC Design Flow and MOS Models question and get a clear, step-by-step explanation grounded in how ELEC4602 is taught and assessed. Read this chapter free, then take your hardest questions to Sia.
