ELEC4602 Chap.10 Semiconductor Memory Design
Semiconductor Memory Design
Week 10 closes the course with dynamic registers and semiconductor memories: ROM, SRAM, DRAM, array organisation, performance, sense amplifiers and floating-gate memory. Each memory family stores information through a different physical mechanism. ROM encodes a programmed connection or state, SRAM maintains a bistable state while powered, and DRAM stores charge that must be sensed and refreshed.
Array organisation adds word lines, bit lines and peripheral circuits, so a cell cannot be evaluated separately from read disturbance, write ability, sensing and the load of the array.
What this chapter covers
- 01
Memory array organisation
- 02
ROM programmed state
- 03
SRAM bistable storage
- 04
DRAM charge storage and refresh
- 05
Read and write paths
- 06
Sense amplifiers and floating-gate memory
Worked example · free
Match a memory cell to its evidence
- +1Match the powered bistable state to SRAM and verify read stability, write ability and interaction with bit-line loading.
- +1Match the fading stored charge to DRAM and verify retention, refresh and the sensing path that detects a small change.
- +1Match the fixed programmed value to ROM and verify that addressing selects the intended stored pattern through the array path.
- +1Explain that array organisation and sense circuitry affect every cell observation, so cell mechanism alone is not complete evidence.
Key terms
- Memory cell
- A memory cell is the repeated circuit element that stores one local information state within an array.
- Word line
- A word line selects a row of memory cells for a read or write operation.
- Bit line
- A bit line carries information between selected cells and the array's peripheral read or write circuitry.
- SRAM
- SRAM stores state in a powered bistable circuit and does not require periodic refresh while power remains.
- DRAM
- DRAM stores information as charge that must be sensed and periodically refreshed.
- Sense amplifier
- A sense amplifier detects a small bit-line difference and regenerates it into a reliable logic-level decision.
Semiconductor Memory Design FAQ
What is the central difference among ROM, SRAM and DRAM?
The storage mechanism differs. ROM represents a programmed state, SRAM maintains a bistable circuit state while powered, and DRAM stores charge that leaks and therefore needs refresh. Those mechanisms determine density, read and write behaviour, peripheral circuitry and the tests needed to demonstrate reliable operation.
Why is a sense amplifier needed in a memory array?
A selected cell may create only a small change on a heavily loaded bit line. The sense amplifier detects and enlarges that difference into a full decision. Its timing and offset can therefore determine whether a correct cell state is read reliably, especially as the array grows.
How should I compare memory cells in an exam answer?
Use storage mechanism, read path, write path, retention requirement, cell complexity and array interaction as common axes. Then name the peripheral circuit that completes the operation. A cell-only drawing is incomplete if the question asks how data is addressed, sensed or restored.
Exam move
Draw one common array frame first: decoder, word line, cell, bit line and sensing path. Place ROM, SRAM and DRAM cells into that same frame so the differences remain tied to a shared read operation. Under each cell, write the physical storage mechanism, whether ordinary rewriting is possible, whether refresh is required and what can disturb the state.
Trace a read from address selection to bit-line response to sense-amplifier decision, then trace a write back into the cell. For SRAM, focus on the competition between preserving state, reading and writing. For DRAM, focus on charge, retention, refresh and the small sensed signal. For ROM, focus on how the programmed pattern becomes a selected output. Finish with array effects: long lines, loading and peripheral timing.
This comparison framework is more useful than memorising isolated cell diagrams because it explains why each family needs different verification evidence. Make a three-operation ledger for read, write and hold. For each, record initial state, selected controls, shared-line condition, observation and required final state. Add an unselected neighbour to every access test so array sharing is verified rather than assumed.
Compare near and distant cells with the same pattern to reveal decoder or line effects, then exchange the stored polarity to expose asymmetry. After proposing a stronger driver or earlier sense decision, rerun the complementary operation and retention check. That final loop detects repairs that solve one access while creating disturbance elsewhere.
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