ELEC4602 Chap.9 Static and Sequential Logic
Static and Sequential Logic
Week 9 extends static CMOS into complex gates, physical layout and sequential storage. Transmission gates and multiplexers steer signals; latches and flip-flops store state according to clock phases; setup and hold describe the timing relationship required around the capturing event. Static and dynamic register structures make different assumptions about how state is retained.
The key reasoning move is to separate logic function from timing behaviour: a circuit may implement the intended Boolean function yet fail when data changes too close to the clock or when a dynamic node is not refreshed correctly.
What this chapter covers
- 01
Complex static CMOS synthesis
- 02
Gate layout and sizing
- 03
Transmission gates and multiplexers
- 04
Latch and flip-flop state
- 05
Setup and hold relationships
- 06
Static versus dynamic storage
Worked example · free
Diagnose a capture failure near the clock edge
- +1Identify the symptom as a timing relationship around capture rather than an error in the steady-state Boolean function.
- +1State that data must remain appropriately stable before and after the capturing event, corresponding to setup and hold boundaries.
- +1Sweep the data transition relative to the clock in controlled steps and observe where capture ceases to be reliable.
- +1Repair the path or clock relationship, then retest the boundary with the implemented load and extracted timing view.
Key terms
- Transmission gate
- A transmission gate uses complementary controlled devices to pass signal levels in either direction when enabled.
- Multiplexer
- A multiplexer selects one of several input paths and connects it to a shared output according to control signals.
- Latch
- A latch is level-sensitive storage whose transparency depends on an active control phase.
- Flip-flop
- A flip-flop captures state around a clock transition using an edge-oriented storage structure.
- Setup time
- Setup time is the required interval for data stability before the capturing clock event.
- Hold time
- Hold time is the required interval for data stability after the capturing clock event.
Static and Sequential Logic FAQ
Why can sequential logic fail when the truth table is correct?
A truth table describes stable logical relationships, not whether a storage element sees valid data at the required time. Clocked circuits add timing constraints, internal state and physical delays. A correct function can therefore fail during capture if data or clock paths violate the storage element's timing boundary.
How are latches and flip-flops different?
A latch is transparent during an active control level and stores when that level changes, while a flip-flop is organised around a clock transition. The distinction changes when data can propagate and how timing paths are analysed. Always describe the control phase or edge with the data path.
What makes a useful setup-and-hold diagram?
Place clock and data on the same horizontal time axis, mark the capturing event and show the stability interval on both sides. Then state whether the tested data movement lies inside or outside that required window. The diagram should explain the relationship, not merely label two waveforms.
Exam move
Separate this week into function, state and time. For function, derive static CMOS or multiplexer behaviour from the conducting path. For state, identify the internal node that retains information and the control condition that makes the element transparent or closed. For time, place data and clock on one axis and mark the capture event, setup side and hold side.
Practise tracing a value through a transmission gate, latch and flip-flop without skipping clock phases. Then create original timing scenarios in which data arrives early, late or changes after capture, and explain the expected outcome. For dynamic storage, add the mechanism that can lose the stored level and the need for refresh or bounded evaluation time.
Finish with verification: sweep relative timing, test both data directions, include the real load and repeat in the post-layout view. This keeps Boolean correctness, storage operation and physical timing evidence distinct. Add a phase table for static, transmission and dynamic implementations. State when each output is driven, conditionally connected, isolated or retained by feedback.
For a sequential path, separate launch, combinational evaluation, arrival, capture and output propagation on one timeline. Vary data position around the clock while keeping load and clock shape fixed, then vary output load with safely captured data. After extraction, compare the same nodes and initial conditions.
This method prevents a capture-window failure from being mislabelled as ordinary delay and keeps phase-order errors distinct from a wrong Boolean network.
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